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The effect of temperature on cache size tuning for low energy embedded systems

Published: 11 March 2007 Publication History

Abstract

Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in these systems. In older technology nodes, active power was the primary contributor to total power dissipation of a CMOS design. However, with the scaling of feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Temperature is a factor which exponentially increases the leakage current. In this paper, we show the effects of temperature on the selection of optimal cache size for low energy embedded systems. Our results show that for a given application, the optimal cache size selection is affected by the temperature. Our experiments have been done for 100nm technology. Our study reveals that the cache size selection for different temperatures depends on the rate at which cache miss increases when reducing the cache size. When the miss rate increases sharply the optimal point is the same for all examined temperatures, however when it becomes smoother, the optimal point for different temperatures begin to get farther.

References

[1]
Zhang C., Vahid F., and Najjar W., A Highly Configurable Cache Architecture for Embedded Systems. ACM Transactions on Embedded Computing Systems, Vol. 4, No. 2, May 2005.
[2]
Albonesi D. H., Selective cache ways: On-demand cache resource allocation, 32nd Annual ACM/IEEE International Symposium on Microarchitecture. 1999.
[3]
Zhang C., Vahid F. and Lysecky R., A self-Tuning Cache Architecture for Embedded Systems. Design Automation and Test Europe, 2004.
[4]
Cai Y. et al. Cache Size Selection for Performance, Energy and Reliability of Time-Constrained Systems, ASP-DAC 2006.
[5]
Tarjan D., Thoziyoor Sh., Jouppi N. P., Cacti 4.0, HP Laboratories, Technical Report, 2006.
[6]
SimpleScalar http://www.simplescalar.com/
[7]
Mibench http://www.eecs.umich.edu/mibench/

Cited By

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  • (2019)Exploring the Role of Large Centralised Caches in Thermal Efficient Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/333985024:5(1-28)Online publication date: 28-Jun-2019
  • (2017)Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.3(75-80)Online publication date: Jan-2017
  • (2012)System-Wide Energy Optimization with DVS and DCRDynamic Reconfiguration in Real-Time Systems10.1007/978-1-4614-0278-7_6(129-163)Online publication date: 30-Mar-2012
  • Show More Cited By

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  1. The effect of temperature on cache size tuning for low energy embedded systems

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 11 March 2007

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    Author Tags

    1. cache memory
    2. embedded systems
    3. leakage current
    4. low energy
    5. temperature-aware design

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    GLSVLSI07
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    GLSVLSI07: Great Lakes Symposium on VLSI 2007
    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    Cited By

    View all
    • (2019)Exploring the Role of Large Centralised Caches in Thermal Efficient Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/333985024:5(1-28)Online publication date: 28-Jun-2019
    • (2017)Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.3(75-80)Online publication date: Jan-2017
    • (2012)System-Wide Energy Optimization with DVS and DCRDynamic Reconfiguration in Real-Time Systems10.1007/978-1-4614-0278-7_6(129-163)Online publication date: 30-Mar-2012
    • (2010)Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time SystemsProceedings of the 2010 23rd International Conference on VLSI Design10.1109/VLSI.Design.2010.22(357-362)Online publication date: 3-Jan-2010

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