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Skew spreading for peak current reduction

Published: 11 March 2007 Publication History

Abstract

This paper presents a circuit optimization technique called skewspreading. Given an edge-triggered sequential circuit, skew spreadingderives the required clock arrival times for all registers so that theskews are distributed evenly in a preselected time window without changing the operating frequency of the circuit. Skew spreading is ideal for peak current reduction, since it distributes clock activities and the ensuing signal activities widely in time. We have developed a skew spreading algorithm and applied it to a suite of benchmark circuits. Simulation results demonstrate that the variance of the resulting skew from the uniform distribution can be reduced to 4% on the average. In comparison to other gate-level peak current reduction techniques, our scheme achieves an average improvement of 17% with a speedup of up to 13.9 times.

References

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R. B. Deokar and S. S. Sapatnekar. A graph-theoretic approach to clock skew optimization. In Proc. Inter. Symp. on Circuits and Systems, pages 407--410, May 1994.
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J. P. Fishburn. Clock skew optimization. IEEE Trans. on Computers, 39(7):945--951, July 1990.
[3]
I. S. Kourtev and E. G. Friedman. Clock skew scheduling for improved reliability via quadratic programming. In IEEE International Conf. on CAD, Nov. 1999.
[4]
W. D. Lam, C.-K. Koh, and C.-W. A. Tsao. Clock scheduling for power supply noise suppression using genetic algorithm with selective gene therapy. In Inter. Symp. on Quality Electronic Design, 2003.
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A. Mukherjee and R. Sankaranarayan. Retiming and clock scheduling to minimize simultaneous switching. In IEEE SOC Conference, Sept. 2004.
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J. L. Neves and E. G. Friedman. Optimal clock skew scheduling tolerant to process variations. In Design Automation Conf., June 1996.
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P. Vuillod, L. Benini, A. Bogliolo, and G. D. Micheli. Clock skew optimization for peak current reduction. In Inter. Symp. on Low Power Electronics and Design, Aug. 1996.

Cited By

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  • (2015)Mixing Drivers in Clock-Tree for Power Supply Noise ReductionIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2015.241177862:5(1382-1391)Online publication date: May-2015
  • (2009)Clock buffer polarity assignment for power noise reductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200918717:6(770-780)Online publication date: 1-Jun-2009
  • (2009)Electronic Design AutomationundefinedOnline publication date: 11-Mar-2009
  • Show More Cited By

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cover image ACM Conferences
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
March 2007
626 pages
ISBN:9781595936059
DOI:10.1145/1228784
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 March 2007

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Author Tags

  1. clock scheduling
  2. clock skew
  3. low power

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GLSVLSI07
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GLSVLSI07: Great Lakes Symposium on VLSI 2007
March 11 - 13, 2007
Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2015)Mixing Drivers in Clock-Tree for Power Supply Noise ReductionIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2015.241177862:5(1382-1391)Online publication date: May-2015
  • (2009)Clock buffer polarity assignment for power noise reductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200918717:6(770-780)Online publication date: 1-Jun-2009
  • (2009)Electronic Design AutomationundefinedOnline publication date: 11-Mar-2009
  • (2008)IR Drop Reduction via a Flip-Flop Resynthesis Technique9th International Symposium on Quality Electronic Design (isqed 2008)10.1109/ISQED.2008.4479702(78-83)Online publication date: Mar-2008

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