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Block placement to ensure channel routability

Published: 11 March 2007 Publication History

Abstract

Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total width/height of the chip and optimal routing area can be obtained. The proposed technique utilizes a piecewise linear model of the channel width. Based on this model, we introduce LP formulation to determine the optimal channel width considering pin alignment by balancing the wire length and the channel width.

References

[1]
M. J. Ciesielski and E. Kinnen, An Analytical Method for Compacting Routing Area in Integrated Circuits, Proc. of 19th DAC, pp.30--37, 1982.
[2]
Y. Kajitani, Order of Channel for Safe Routing and Optimal Compaction of Routing Area, IEEE Trans. on CAD, Vol.2, No.4, pp.293--300, 1983.
[3]
David P. La Potin and Stephen W. Director, Mason: A Global Floorplanning Approach for VLSI Design, IEEE Trans. on CAD, Vol.5, No.4, pp.477--489, 1986.
[4]
Yang Cai and D. F. Wong, Channel/Switchbox Definition for VLSI Building-Block Layout, IEEE Trans. on CAD, Vol.10, No.12, pp.1485--1493, 1991.
[5]
Jin-Tai Yan, Routing Space Estimation and Safe Assignment for Macro Cell Placement Proc. of ASPDAC 1995, pp.851--856, 1995.
[6]
Nikolas G., B.-M. Mortazavi, An Efficient Building Block Layout Methodology for Compact Placement Proc. of GLSIVLSI 1995, pp.118--123, 1995.
[7]
H. Murata, S. Nakatake, K. Fujiyoshi, and Y. Kajitani, VLSI module placement based on rectangle-packing by Sequence-Pair, IEEE Trans. on CAD, Vol.15, No.12, pp.1518--1524, 1996.
[8]
Jun Dong Cho, Wire Space and Length Estimation in Two-Dimensional Arrays, IEEE Trans. on CAD, Vol.19, No.5, pp.612--615, 2000.
[9]
Yiaoyu Song, Qian-Yu Tang, Dian Zhou, and Yuke Wang, Wire Space Estimation and Routability Analysis, IEEE Trans. on CAD, Vol.19, No.5, pp.624--628, 2000.

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  1. Block placement to ensure channel routability

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
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      New York, NY, United States

      Publication History

      Published: 11 March 2007

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      Author Tags

      1. channel
      2. placement
      3. routability
      4. routing space

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      GLSVLSI07: Great Lakes Symposium on VLSI 2007
      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

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