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Physical aware clock skew rescheduling

Published: 11 March 2007 Publication History

Abstract

Yield driven skew scheduling method leads to a clock tree with much greater wire length and buffer number that is not acceptable by designer. Geometry based register position relationships are converted to skew constraints and are combined with timing constraints harmoniously. With the two kinds of skew constraints together, our algorithm solves the skew scheduling problem for both restrictions and gives safety margins for not only timing variations but clocktree wire variations. It makes the yield driven clock network realizable inpractical design. Experimental results show that our algorithm has 72.7% yield improvement then normal scheduling. In addition, the clock tree wire length and buffer number are reduced by 52.2% and 40.4% compared with previous yielddriven skew scheduling method.

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Cited By

View all
  • (2015)Multi-parameter clock skew schedulingIntegration, the VLSI Journal10.1016/j.vlsi.2014.07.00548:C(129-137)Online publication date: 1-Jan-2015
  • (2010)Register relocation to optimize clock network for multi-domain clock skew schedulingProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537941(3180-3183)Online publication date: May-2010
  • (2008)Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield ImprovementProceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.69(467-470)Online publication date: 7-Apr-2008
  • Show More Cited By

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
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    Publication History

    Published: 11 March 2007

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    Author Tags

    1. clock skew
    2. process variations
    3. skew rescheduling

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    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    Cited By

    View all
    • (2015)Multi-parameter clock skew schedulingIntegration, the VLSI Journal10.1016/j.vlsi.2014.07.00548:C(129-137)Online publication date: 1-Jan-2015
    • (2010)Register relocation to optimize clock network for multi-domain clock skew schedulingProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537941(3180-3183)Online publication date: May-2010
    • (2008)Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield ImprovementProceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.69(467-470)Online publication date: 7-Apr-2008
    • (2008)Multi-Objective Statistical Yield Enhancement using Evolutionary AlgorithmProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.71(472-479)Online publication date: 3-Sep-2008

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