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- Yang LFan BCong MZhao J(2010)Register relocation to optimize clock network for multi-domain clock skew schedulingProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537941(3180-3183)Online publication date: May-2010
- Mirsaeedi MZamani MSaeedi M(2008)Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield ImprovementProceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.69(467-470)Online publication date: 7-Apr-2008
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