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Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath

Published: 11 March 2007 Publication History

Abstract

In this paper, we propose an extended model of register-sharing in a dual-rail two-phase asynchronous datapath, which provides us with a larger solution space of resource sharing. We introduce a new type of register which is driven by data to be latched and a control signal. By using this type of register, multiple data can share the same register aggressively in a dual-rail two-phase asynchronous datapath.

References

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H. Kagotani, T. Nanya, "Synthesis of Two-Phase Quasi-Delay-Insensitive Circuits from Dependence Graphs," IEICE Trans. Information and Systems, Vol.J77-D-I, No.8, pp.548--556, 1994.
[2]
T. Nanya, Y. Ueno, H. Kagotani, M. Kuwako, A. Takamura, "TITAC : Design of a quasi-delay-insensitive microprocessor," IEEE Des. Test Comput., vol.11, no.2, pp.50--63, 1994.
[3]
S. Saito, N. Watanabe, A. Masaki, "An Architecture of FPGA for Dual-Rail Two-Phase Asynchronous Circuits," IEICE Trans. Information and Systems, Vol.J86-D-I, No.2, pp.108--116, 2003.
[4]
B. M. Bachman, H. Zheng, C. Merys, "Architectural Synthesis of Timed Asynchronous Systems," Proc. International Conf. Computer Design, pp.354--363, 1999.
[5]
H. Saito, T. Yoneda, "Asynchronous Data-Path Circuit Synthesis by Using Force-Directed Scheduling Algorithm and Consideration to Improve Efficiency", Technical Report of IEICE, VLD2004-80, Vol.2004, No.80, pp.115--120, 2004.
[6]
S. F. Nielsen, J. Sparso, J. Madsen, "Towards behavioral synthesis of asynchronous circuits - an implementation template targeting syntax directed compilation," Proc. EUROMICRO Systems on Digital System Design, pp.298--305, 2004.
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M. Theobald, S. M. Nowick, "Transformations for the Synthesis and Optimization of Asynchronous Distributed Control", Proc. Design Automation Conference, pp.263--268, 2001.
[8]
K. Ohashi, M. Kaneko, "Statistical Analysis Driven Synthesis of Asynchronous Systems," Proc. International Conf. Computer Design, pp.200--205, 2005.

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  1. Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
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      Published: 11 March 2007

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      Author Tags

      1. asynchronous circuit
      2. datapath
      3. high-level synthesis
      4. register binding

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      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

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