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On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors

Published: 11 March 2007 Publication History

Abstract

Applications running on Multiprocessor Systems-on-Chips (MP-SoCs) exhibit complex interaction patterns, resulting in significant amounts of time spent while synchronizing for mutually exclusive access to shared resources. Such an overhead is expected to increase with the degree of parallelism and with the mutual correlation of concurrent tasks, thus becoming in a severe obstacle to the full exploitation of a system potential. Although the topic has been extensively studied in the literature, in MPSoC architectures, which exhibit different tradeoffs with respect to traditional multi-processors, the available results may not be valid or hold only partially. Furthermore, the strict energy budget of MPSoCs requires also the evaluation of the energy efficiency of such synchronization primitives. In this work we survey various state-of-the-art implementations of synchronization primitives, in order to assess their impact on performance and on energy consumption. The results of our analysis show that some commonly accepted intuitions in the multiprocessor domain do not hold in the context of MPSoCs.

References

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T. E. Anderson, "The Performance of Spin Lock Alternatives for Shared-Memory Multiprocessors," IEEE Transactions on Parallel and Distributed Systems, Vol. 1, No. 1, pp. 6--16, Jan. 1990.
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G. Graunke, S. Thakkar, "Synchronization Algorithms for Shared-Memory Multiprocessors," IEEE Computer, Vol. 23, No. 6, pp. 60--69, Jun. 1990.
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J. M. Mellor-Crummey, M. Scott, "Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors," ACM Transactions on Computer Systems, Vol. 2, No. 1, pp. 21--65, Feb. 1991.
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J. Li, J. F. Martinez, M. C. Huang, "The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors," High Performance Computer Architecture, 2004. HPCA-10. Proceedings. 10th International Symposium on HPCA-10: Proceedings of 10th International Symposium on High Performance Computer Architecture, pp. 14--23, Feb. 2004.
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David Geer, "Industry Trends: Chip Makers Turn to Multicore Processors," IEEE Computer, Vol. 38, No. 5, pp. 11--13, May 2005.
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D. Lackey, et al., "Managing Power and Performance for SOC Designs using Voltage Islands," ICCAD 2002: ACM/IEEE International Conference on CAD, pp. 195--202, Nov. 2002.
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"A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor," T. Hattori, et al., ISSCC'06: IEEE International Solid-State Circuits Conference, Feb. 2006.
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Cited By

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  • (2019)Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715266(552-557)Online publication date: Mar-2019
  • (2018)Low-cost and energy-efficient distributed synchronization for embedded multiprocessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202236118:8(1257-1261)Online publication date: 29-Dec-2018
  • (2014)$C\!\!-\!\!Lock$ : Energy Efficient Synchronization for Embedded Multicore SystemsIEEE Transactions on Computers10.1109/TC.2013.8463:8(1962-1974)Online publication date: Aug-2014
  • Show More Cited By

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cover image ACM Conferences
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
March 2007
626 pages
ISBN:9781595936059
DOI:10.1145/1228784
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 March 2007

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Author Tags

  1. energy
  2. multiprocessor
  3. synchronization
  4. system-on-chip

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GLSVLSI07: Great Lakes Symposium on VLSI 2007
March 11 - 13, 2007
Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2019)Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715266(552-557)Online publication date: Mar-2019
  • (2018)Low-cost and energy-efficient distributed synchronization for embedded multiprocessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202236118:8(1257-1261)Online publication date: 29-Dec-2018
  • (2014)$C\!\!-\!\!Lock$ : Energy Efficient Synchronization for Embedded Multicore SystemsIEEE Transactions on Computers10.1109/TC.2013.8463:8(1962-1974)Online publication date: Aug-2014
  • (2013)HPC runtime support for fast and power efficient locking and synchronization2013 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER.2013.6702659(1-7)Online publication date: Sep-2013
  • (2012)Energy optimization of representative barrier algorithmsJournal of Central South University10.1007/s11771-012-1348-z19:10(2823-2831)Online publication date: 4-Oct-2012
  • (2009)Energy-optimal synchronization primitives for single-chip multi-processorsProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531578(141-144)Online publication date: 10-May-2009
  • (2008)Distributed and low-power synchronization architecture for embedded multiprocessorsProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450153(73-78)Online publication date: 19-Oct-2008

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