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Improvements for constraint solving in the systemc verification library

Published: 11 March 2007 Publication History

Abstract

For verification of complex system-on-chip designs often constraint-based randomization is used. This allows to simulate scenarios that may be difficult to generate manually. For the system description language SystemC the SystemC Verification (SCV) Library has been introduced. Besides advanced verification features like data introspection and transaction recording the SCV library enables constraint-based randomization forSystemC models. However, the SCV library has two disadvantages that restrict their practical use: There is no support of bit operators in SCV constraintsand the SCV constraint solver cannot guarantee a uniform distribution of the constraint solutions. In this paper we provide a detailed analysis of these problems and present solutions that have been integrated in the library.

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Cited By

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  • (2014)Simplified stimuli generation for scenario and assertion based verification2014 15th Latin American Test Workshop - LATW10.1109/LATW.2014.6841904(1-6)Online publication date: Mar-2014
  • (2012)A testbench specification language for SystemC verificationProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380499(333-342)Online publication date: 7-Oct-2012
  • (2012)The system verification methodology for advanced TLM verificationProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380497(313-322)Online publication date: 7-Oct-2012
  • Show More Cited By

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cover image ACM Conferences
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
March 2007
626 pages
ISBN:9781595936059
DOI:10.1145/1228784
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 March 2007

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Author Tags

  1. constraint-based randomization
  2. systemC
  3. systemC verification library

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GLSVLSI07: Great Lakes Symposium on VLSI 2007
March 11 - 13, 2007
Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2014)Simplified stimuli generation for scenario and assertion based verification2014 15th Latin American Test Workshop - LATW10.1109/LATW.2014.6841904(1-6)Online publication date: Mar-2014
  • (2012)A testbench specification language for SystemC verificationProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380499(333-342)Online publication date: 7-Oct-2012
  • (2012)The system verification methodology for advanced TLM verificationProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380497(313-322)Online publication date: 7-Oct-2012
  • (2012)CRAVE: An advanced constrained random verification environment for SystemC2012 International Symposium on System on Chip (SoC)10.1109/ISSoC.2012.6376356(1-7)Online publication date: Oct-2012
  • (2010)SMT-based Stimuli Generation in the SystemC Verification LibraryAdvances in Design Methods from Modeling Languages for Embedded Systems and SoC’s10.1007/978-90-481-9304-2_14(227-244)Online publication date: 3-Aug-2010
  • (2010)ESL Design and VerificationDebugging at the Electronic System Level10.1007/978-90-481-9255-7_2(9-31)Online publication date: 19-May-2010
  • (2009)Overcoming limitations of the SystemC data introspectionProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874764(590-593)Online publication date: 20-Apr-2009
  • (2009)Debugging Contradictory Constraints in Constraint-Based Random SimulationLanguages for Embedded Systems and their Applications10.1007/978-1-4020-9714-0_18(273-290)Online publication date: 2009
  • (2008)Partial order reduction for scalable testing of systemC TLM designsProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391706(936-941)Online publication date: 8-Jun-2008
  • (2008)Contradiction analysis for constraint-based random simulation2008 Forum on Specification, Verification and Design Languages10.1109/FDL.2008.4641434(130-135)Online publication date: Sep-2008

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