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Systematic design of two-stage operational amplifiers based on settling time and open-loop constraints

Published: 11 March 2007 Publication History

Abstract

Considering the importance of settling behavior of operational amplifiers (opamps) for a given accuracy in many applications, an efficient methodology for the design of high-speed two-stage opamps, based on settling time, is proposed in this paper. Concerning the application of the opamp, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. Simulation results are presented to show the effectiveness of the methodology.

References

[1]
P. J. Hurst, et al. "Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers", IEEE Trans. Circuits and Systems I, Vol. 51, no. 2, pp. 275--285, Feb. 2004.
[2]
R. Lotfi, M. Taherzadeh, M. Yaser Azizi, O. Shoaei, "Low Power Design for Low-voltage Fast-settling Operational Amplifier in Switched Capacitor Applications," INTEGRATION VLSI journal, Vol. 36, Aug. 2003, 175--189.
[3]
H. Aminzadeh, M. Danaie, and R. Lotfi, "A Low-Power Design Methodology for Single-Stage Operational Amplifiers," in Proc. IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Technology, pp.62--67, Sept. 5--7, 2006.
[4]
H. Aminzadeh, and R. Lotfi, "Open-Loop Analysis of Cascode Compensation," in Proc. IEEE NEWCAS, pp. 81--84, June 2006.
[5]
A. Marques, et al., "Settling time analysis of third order systems", Proc. IEEE Int. Conf. on Electronics, Circuits and Systems, Vol. 2, pp. 505--508, 1998.

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
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    Publication History

    Published: 11 March 2007

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    Author Tags

    1. design methodology
    2. frequency compensation
    3. operational amplifiers
    4. settling time
    5. stability
    6. switched-capacitor circuits

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    GLSVLSI07: Great Lakes Symposium on VLSI 2007
    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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