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Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology

Published: 11 March 2007 Publication History

Abstract

Clustered sleep transistor insertion is an effective leakage power reduction technique that is well-suited for integration in an automated design flow and offers a flexible tradeoff between area, delay overhead and turn-on transition time. In this work, we focus on the design of a family of sleep transistor cells, fully compatible with the physical design rules of a commercial 65nm CMOS library. We describe circuit-level and layout optimizations, as well as the cell characterization procedure required to support automated sleep transistor cell selection and instantiation in a clustered power-gating insertion flow.

References

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K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits", Proceedings of the IEEE, Vol. 91, No. 2, pp. 305--327, 2003.
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F. Fallah, M. Pedram, "Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits," IEICE Transactions on Electronics, Vol. E88-C, No 4, pp.509--519, 2005.
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V. Khandelwal, A. Srivastava, "Leakage control through fine-grained placement and sizing of sleep transistors," ICCAD-04: IEEE/ACM International Conference on CAD, pp. 533--536, San Jose, CA, 2004.
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M. Anis, S. Areibi, M. Elmasry, "Design and optimization of multithreshold CMOS (MTCMOS) circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 10, pp. 1324--1342, 2003.
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P. Babighian, L. Benini, A. Macii, E. Macii, "Post-layout leakage power minimization based on distributed sleep transistor insertion," ISLPED-04: ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 138--143, Newport Beach, CA, 2004.
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STMicroelectronics CORE65LPSVT_1.00V 4.0 Standard Cell Library User Manual & Data Book.
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  • (2019)Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error DetectionJournal of Low Power Electronics and Applications10.3390/jlpea90200179:2(17)Online publication date: 21-Apr-2019
  • (2019)On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-ScalingVLSI-SoC: Opportunities and Challenges Beyond the Internet of Things10.1007/978-3-030-15663-3_8(153-177)Online publication date: 17-May-2019
  • (2018)Row-based power-gatingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203544819:3(469-482)Online publication date: 29-Dec-2018
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  1. Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 11 March 2007

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    Author Tags

    1. insertion
    2. layout
    3. leakage power
    4. sleep transistor
    5. standard-cell

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    March 11 - 13, 2007
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    Cited By

    View all
    • (2019)Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error DetectionJournal of Low Power Electronics and Applications10.3390/jlpea90200179:2(17)Online publication date: 21-Apr-2019
    • (2019)On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-ScalingVLSI-SoC: Opportunities and Challenges Beyond the Internet of Things10.1007/978-3-030-15663-3_8(153-177)Online publication date: 17-May-2019
    • (2018)Row-based power-gatingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203544819:3(469-482)Online publication date: 29-Dec-2018
    • (2017)Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-HoppingVLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability10.1007/978-3-319-67104-8_8(152-172)Online publication date: 1-Sep-2017
    • (2014)Power-Gating for Leakage Control and BeyondCircuit Design for Reliability10.1007/978-1-4614-4078-9_9(175-205)Online publication date: 16-Oct-2014
    • (2011)Power Efficient Variability Compensation Through Clustered Tunable Power-GatingIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2011.21636891:3(242-253)Online publication date: Oct-2011
    • (2010)NBTI-Aware Clustered Power GatingACM Transactions on Design Automation of Electronic Systems10.1145/1870109.187011216:1(1-25)Online publication date: 1-Nov-2010
    • (2010)Analysis of NBTI-induced SNM degradation in power-gated SRAM cellsProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537452(785-788)Online publication date: May-2010
    • (2009)NBTI-aware power gating for concurrent leakage and aging optimizationProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594264(127-132)Online publication date: 19-Aug-2009
    • (2009)NBTI-aware sleep transistor design for reliable power-gatingProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531618(333-338)Online publication date: 10-May-2009
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