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A high-level register optimization technique for minimizing leakage and dynamic power

Published: 11 March 2007 Publication History

Abstract

A large fraction of the total power dissipated in a digital circuit is consumed by the clocked elements in the data-path. Hence, savings in power usage of these components can be directly reflected in a circuit's overall power consumption. Reducing power through techniques that optimize power consumption in combinational elements has been extensively discussed in the existing literature. However, these techniques cannot be applied for reducing the power in sequential elements. In this work, we focus on this problem, and introduce a novel cluster-based register optimization technique that is employed in High-Level Synthesis (HLS) with Power Islands. Our experiments conducted on several synthesis benchmarks implemented at the transistor level using a 65 nm process technology showed anaverage reduction of 18% in total power consumption due to our technique with no or little area overhead.

References

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L. Benini, P. Siegel, and G.D. Micheli. Saving Power by Synthesizing Gated Clocks for Sequential Circuits. IEEE Design and Test of Computers, 11(4):32--41, 1994.
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Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu. New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design. In Proceedings of Custom Integrated Circuits Conference, 2000.
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D. Dal, D. Kutagulla, A. Nunez, and N. Mansouri. Power Islands: A High-Level Synthesis Technique for Reducing Spurious Switching Activity and Leakage. In MWSCAS'05: IEEE International Midwest Symposium on Circuits and Systems, 2005.
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D. Dal, A. Nunez, and N. Mansouri. Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron. In ISQED'06: 7th International Symposium on Quality Electronic Design, 2006.
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C. Gopalakrishnan and S. Katkoori. Resource Allocation and Binding Approach for Low Leakage Power. In 16th International Conference on VLSI Design, 2003.
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G.D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc, Hightstown, NJ, 1994.
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P. Parakh, D. Mullassery, A. Chandrashekar, H. Koc, D. Dal, and N. Mansouri. Interconnect-centric High-Level Synthesis for Enhanced Layouts with Reduced Wire Length. In MWSCAS'06: IEEE International Midwest Symposium on Circuits and Systems, 2006.
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Cited By

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  • (2009)Better than optimum?Proceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531617(327-332)Online publication date: 10-May-2009
  • (2008)Determining the Optimal Number of Islands in Power Islands SynthesisProceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.42(22-27)Online publication date: 7-Apr-2008

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  1. A high-level register optimization technique for minimizing leakage and dynamic power

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      New York, NY, United States

      Publication History

      Published: 11 March 2007

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      Author Tags

      1. DSM
      2. HLS
      3. high level synthesis
      4. leakage
      5. partitioning
      6. power islands
      7. register optimization

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      GLSVLSI07: Great Lakes Symposium on VLSI 2007
      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

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      Cited By

      View all
      • (2009)Better than optimum?Proceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531617(327-332)Online publication date: 10-May-2009
      • (2008)Determining the Optimal Number of Islands in Power Islands SynthesisProceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.42(22-27)Online publication date: 7-Apr-2008

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