An efficient net ordering algorithm for buffer insertion
Abstract
References
Index Terms
- An efficient net ordering algorithm for buffer insertion
Recommendations
An efficient surface-based low-power buffer insertion algorithm
ISPD '05: Proceedings of the 2005 international symposium on Physical designBuffer insertion is an important technique used to achieve timing closure in high performance VLSI designs. As the number of buffers in ASIC designs has increased with process scaling, the power con-sumption of buffers has become a critical concern. In ...
An O(bn2) time algorithm for optimal buffer insertion with b buffer types
Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer insertion algorithm of van Ginneken has a time complexity of O(n2), where n is the number of buffer positions. Lillis, Cheng, and Lin extended van Ginneken's ...
Circuit-wise buffer insertion and gate sizing algorithm with scalability
DAC '08: Proceedings of the 45th annual Design Automation ConferenceMost existing buffer insertion algorithms, such as van Ginneken's algorithm, consider individual nets and therefore often result in high buffer cost due to lack a global view. Thus, circuit-wise buffering is necessary to reduce buffer cost. Recently, ...
Comments
Information & Contributors
Information
Published In
- General Chairs:
- Hai Zhou,
- Enrico Macii,
- Program Chairs:
- Zhiyuan Yan,
- Yehia Massoud
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Check for updates
Author Tags
Qualifiers
- Article
Conference
Acceptance Rates
Upcoming Conference
- Sponsor:
- sigda
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 196Total Downloads
- Downloads (Last 12 months)1
- Downloads (Last 6 weeks)0
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in