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View all- Jahanian ASaheb Zamani MSafizadeh H(2011)Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodologyIntegration, the VLSI Journal10.1016/j.vlsi.2010.10.00144:2(123-135)Online publication date: 1-Mar-2011
- Jahanian ASaheb Zamani M(2010)Chip master planning: An efficient methodology to improve design closure and complexity management of ultra large chips2010 15th CSI International Symposium on Computer Architecture and Digital Systems10.1109/CADS.2010.5623543(107-114)Online publication date: Sep-2010
- Jahanian ASaheb Zamani MLombardi FBhanja SMassoud YBahar R(2009)Improved performance and yield with chip master planning design methodologyProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531590(185-190)Online publication date: 10-May-2009
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