skip to main content
10.1145/1228784.1228916acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Improved timing closure by early buffer planning in floor-placement design flow

Published: 11 March 2007 Publication History

Abstract

Buffer insertion plays an increasingly critical role on circuit performance and signal integrity especially in deep submicron technologies. Buffer insertion stage is very important for buffering efficiency. Early buffer insertion may cause misestimating due to unknown cell locations whereas buffer insertion after placement may not be very effective because the cell locations are fixed and buffer resources may be distributed inappropriately.In this paper, a buffer planning algorithm for floor-placement design flow is presented which creates a map of buffer requirements in various regions of the design at the floorplanning stage based on the statistical distribution of critical paths and enforces the placer to distribute white spaces with respect to the estimated buffer requirement map.Experimental results show that the proposed method improves the performance of experimented circuits with smaller number of buffers and better power consumption compare to conventional methods. Furthermore, power-delay product has been improved considerably, especially for large circuits with a small growth in CPU time.

References

[1]
Cong, J. Challenges and opportunities for design innovations in nanometer technologies. SRC Design Sciences Concept Paper, 1997.
[2]
Alpert, C. J., and Hu, J., and Sapatnekar, S. S. and Villarrubia, P. G. A Practical Methodology for Early Buffer and Wire Resource Allocation. In IEEE Transactions on CAD, Vol. 22, No. 5, 2003.
[3]
Cong, J., and Kong, T., and Pan, D. Z. Buffer block planning for interconnect driven floorplanning. In IEEE/ACM International Conference on CAD, 1999, 54--57.
[4]
Sarkar, P., and Sundararaman, V., and Koh, C. K. Routability-driven Repeater Block Planning for Interconnect-centric Floorplanning. In International Symposium on Physical Design, 2000, 186--191.
[5]
Dragan, F. F., and Kahng, A. B., and Mandoiu, I., and Muddu, S. Provably good global buffering using an available buffer block plan. In Proc. IEEE/ACM International Conference on Computer-Aided Design, 2000, 104--109.
[6]
Tang, X., and Wong, D. F. Planning buffer locations by network flow. In Proc. ISPD, 2000, 180--185.
[7]
Ma, Y., and Hong, X., and Dong, S. Buffer Planning as an Integral Part of Floorplanning with Consideration of Routing Congestion. In IEEE Transactions on CAD, May 2005, 609--621.
[8]
Sham C. W., Wong, W. C., and Young, E. F. Y. Congestion estimation with buffer planning in floorplan design. In Proc. Design Automation and Test in Europe, 2000, 1--6.
[9]
Garcea, G. S., and Van der Mejis, N.P., and Otten, R. H. J. M. Statistically aware buffer planning. In Design Automation and Test in Europe, 2004, 1402--1403.
[10]
Cheng, Y. H., and Chang, Y.W. Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. In ASP-DAC, 2004, 624--627.
[11]
Jahanian A., and Saheb Zamani, M. Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. In International Symposium on Very Large Scale Integrated Circuits, 2005, 411--415.
[12]
Hill, D., and Kahng, A.B. RTL to GDSII-From Foilware to Standard Practice. In IEEE Design & Test of Computers, January-February, 2004, 9--12.
[13]
Roy, J. A., and Adya, S., and Papp, D.A., and Markov, I. Min-cut floorplacement. In IEEE Transactions on CAD, 2005, 1313--1326.
[14]
Chen, H., and Qiao, C., and Zhou, F., and Cheng, C. K. Refined single trunk tree: a rectilinear Steiner tree generator for interconnect prediction. In SLIP, 2002, 85--89.
[15]
Saeedi, M., and Saheb Zamani, M., and and Jahanian, A. Prediction and reduction of routing congestion. In ACM International Symposium on Physical Design, 2006, 72--77.
[16]
IWLS Benchmarks, Available on http://iwls.org/iwls2005/benchmarks.html, 2005.
[17]
Magma Design Automation, A Complete Design Solution for Structured ASICs. http://www.magma-da.com, Dec 2005.

Cited By

View all
  • (2011)Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodologyIntegration, the VLSI Journal10.1016/j.vlsi.2010.10.00144:2(123-135)Online publication date: 1-Mar-2011
  • (2010)Chip master planning: An efficient methodology to improve design closure and complexity management of ultra large chips2010 15th CSI International Symposium on Computer Architecture and Digital Systems10.1109/CADS.2010.5623543(107-114)Online publication date: Sep-2010
  • (2009)Improved performance and yield with chip master planning design methodologyProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531590(185-190)Online publication date: 10-May-2009
  • Show More Cited By

Index Terms

  1. Improved timing closure by early buffer planning in floor-placement design flow

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 11 March 2007

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. buffer insertion
      2. buffer planning
      3. design convergence

      Qualifiers

      • Article

      Conference

      GLSVLSI07
      Sponsor:
      GLSVLSI07: Great Lakes Symposium on VLSI 2007
      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

      Acceptance Rates

      Overall Acceptance Rate 312 of 1,156 submissions, 27%

      Upcoming Conference

      GLSVLSI '25
      Great Lakes Symposium on VLSI 2025
      June 30 - July 2, 2025
      New Orleans , LA , USA

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)4
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 27 Jan 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2011)Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodologyIntegration, the VLSI Journal10.1016/j.vlsi.2010.10.00144:2(123-135)Online publication date: 1-Mar-2011
      • (2010)Chip master planning: An efficient methodology to improve design closure and complexity management of ultra large chips2010 15th CSI International Symposium on Computer Architecture and Digital Systems10.1109/CADS.2010.5623543(107-114)Online publication date: Sep-2010
      • (2009)Improved performance and yield with chip master planning design methodologyProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531590(185-190)Online publication date: 10-May-2009
      • (2008)An integrated nonlinear placement framework with congestion and porosity aware buffer planningProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391651(702-707)Online publication date: 8-Jun-2008
      • (2008)Performance and Timing Yield Enhancement using Highway-on-Chip PlanningProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.116(165-172)Online publication date: 3-Sep-2008

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media