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An effective buffer planning algorithm for IP based fixed-outline SOC placement

Published: 11 March 2007 Publication History

Abstract

More and more IP cores are used in modern SOC designing. In order to place IP cores effectively, hierarchical design has been introduced and better supported by fixed-outline floorplanning than outline-free [1]. In this paper, we also consider buffer insertion issue in fixed-outline floorplanning with the help of the Less Flexibility First (LFF) algorithm, which runs in a fixed-outline area and places IP cores as hard modules one after another with no backtracks. Unlike Simulated Annealing (SA), LFF is a deterministic packing algorithm and runs without topological representations. Therefore, it is able to tell the difference among geometric floorplans with the same topological structure, which is helpful to get a better result for buffer planning since buffer insertions are quite sensitive to a geometric change. Moreover, a 2-staged packing and a post greedy method after packing are also introduced based on a net-classing strategy and finally help to achieve great success rate improvement of buffer insertion (about +40.7% in 0.18um and +37.1% in 0.07μm). Meanwhile, our buffer planning method runs much faster than SA, since it is deterministic and has no backtracks. Besides, it is also useful to provide an initial solution for SA for further optimization.

References

[1]
Saurabh N. Adya and Igor L. Markov, "Fixed-Outline Floorplanning: Enabling Hierarchical Design," IEEE Trans. on VLSI Systems, vol. 11, no. 6, pp. 1120--1135, Dec. 2003.
[2]
Jarrod A. Roy., Saurabh N. Adya., David A. Papa. and Igor L. Markov, "Min-cut Floorplacement," to appear in IEEE Trans. on CAD, 2006.
[3]
J. Cong, T. Kong, and D. Z. Pan, "Buffer block planning for interconnect driven floorplanning," in Proc. International. Conference of Computer-Aided Design, pp.358--363, Nov. 1999.
[4]
P. Sarkar, V. Sundararaman, and C. K. Koh, "Routability-driven repeater block planning for interconnect-centric floorplanning," in Proc. International Symposium of Physical Design, pp.186--191, 2000.
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Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, et al, "A buffer planningalgorithm based on dead space redistribution," in Proc. IEEE ASPDAC'03, pp.435--438, Jan. 2003.
[11]
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao, "Simultaneous Floorplanning and Buffer Block Planning," in Proc. IEEE ASPDAC'03, pp.431--434, Jan. 2003.
[12]
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, C. K. Cheng and Jun Gu, "Buffer planning as an integral part of floorplanning with consideration of routing congestion," IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, Vol. 24, No. 4, Arpil 2005.
[13]
Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu, "VLSI Block Placement Using Less Flexibility First Principles," in Proc. IEEE ASPDAC'01, Jan. 2001, pp.601--604.
[14]
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J. Cong and Z. Pan, "Interconnect performance estimation models for design planning," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 20, no. 6, pp. 739--752, Jun. 2001.

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  1. An effective buffer planning algorithm for IP based fixed-outline SOC placement

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
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      Published: 11 March 2007

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      Author Tags

      1. buffer planning
      2. fixed-outline
      3. floorplanning
      4. very large scale integration (VLSI)

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      March 11 - 13, 2007
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