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RT-level vector selection for realistic peak power simulation

Published: 11 March 2007 Publication History

Abstract

We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with the accuracy of low-level power simulation. We rely on efficient RT-level peak power prediction heuristics to select a handful of input vector pairs from the simulation testbench. These vector pairs are highly likely to induce the worst-case peak power. After that, the low-level power simulation is performed only with these peak power candidate vector pairs to obtain the realistic peak power values. Computationally, there are three major stages in our methodology. Firstly, we analyze the structure of the circuit and calculate the peak power weight for each input pin so as to construct a so-called mountain-based model. Secondly, we perform waveform composition to compute the peak power metric for each given input vector pair. Finally, we select a few candidate vectors for low-level power simulation. By doing so, the time-consuming simulation at the low levels can be mostly avoided without losing accuracy. Experiment results show that only less than 1% of the total functional patterns defined in a testbench are needed to be selected for low-level power simulation in order to catch the worst-case peak power vector pair.

References

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Cited By

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  • (2015)STG-based detection of power virus inputs in FSM2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2015.7282039(1-4)Online publication date: Aug-2015
  • (2011)Accelerating dynamic peak power analysis using an essential-signal-based methodologyProceedings of 2011 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2011.5783596(1-5)Online publication date: Apr-2011

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 11 March 2007

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    Author Tags

    1. peak power estimation
    2. power modeling
    3. vector selection

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    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    • (2015)STG-based detection of power virus inputs in FSM2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2015.7282039(1-4)Online publication date: Aug-2015
    • (2011)Accelerating dynamic peak power analysis using an essential-signal-based methodologyProceedings of 2011 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2011.5783596(1-5)Online publication date: Apr-2011

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