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A fast clock scheduling for peak power reduction in LSI

Published: 11 March 2007 Publication History

Abstract

The reduction of the peak power consumption of LSI is required to reduce the instability of gate operation, the delay increase, the noise and etc. It is possible to reduce the peak power consumption by clock scheduling because it controls the switching timings of registers and combinational logic elements. In this paper, we propose a fast power estimation method for the clock scheduling and fast clock scheduling methods for the peak power reduction. In experiments, it is shown that the peak power wave estimated by the proposed method in a few seconds is highly correlated with the peak power wave obtained by HSPICE simulation in several days. By using the proposed power estimation method, the proposed clock scheduling method finds clock schedules for benchmark circuits that greatly reduce the peak power in a few minutes.

References

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A. Takahashi. Practical Fast Clock-Schedule Design Algorithms. IEICE Trans. Fundamentals, E89-A(4):1005--1011, 2006.
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R. B. Deoker and S. S. Sapatneker. A Graph-Theoretic Approach to Clock Skew Optimization. In ISCAS, pages 407--410, 1994.
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J. Fishburn. Clock skew optimization. IEEE Trans. on Computers, 39(7):945--951, 1990.
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K. Kurokawa, T. Yasui, Y. Matsumura, M. Toyonaga, and A. Takahashi. A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling. IEICE Trans. Fundamentals, E85-A(12):2746--2755, 2002.
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W.-C. D. Lam, C.-K. Koh, and C.-W. A. Tsao. Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. In ISQED, pages 327--332, 2003.
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A. Takahashi and Y. Kajitani. Performance and reliability driven clock scheduling of sequential logic circuits. In ASP-DAC'97, pages 37--43, 1997.
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P. Vuilod, L. Benini, A. Bogliolo, and G. DeMIcheli. Clock-skew optimization for peak current reduction. In ISLPED, pages 265--270, 1996.

Cited By

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  • (2022)Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured CellsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2021VLP0014E105.A:3(487-496)Online publication date: 1-Mar-2022

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cover image ACM Conferences
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
March 2007
626 pages
ISBN:9781595936059
DOI:10.1145/1228784
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 March 2007

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Author Tags

  1. clock scheduling
  2. general-synchronous framework
  3. peak power reduction
  4. power consumption estimation

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GLSVLSI07
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GLSVLSI07: Great Lakes Symposium on VLSI 2007
March 11 - 13, 2007
Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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View all
  • (2022)Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured CellsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2021VLP0014E105.A:3(487-496)Online publication date: 1-Mar-2022

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