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Integrated placement for mixed macro cell and standard cell designs
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE conference on Design automation table of contents
Orlando, Florida, United States
Pages: 32 - 35  
Year of Publication: 1991
ISBN:0-89791-363-9
Authors
Michael Upton  Seattle Silicon Corporation
Khosrow Samii  Seattle Silicon Corporation
Stephen Sugiyama  Seattle Silicon Corporation
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 13,   Citation Count: 6
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ABSTRACT

This paper presents an approach to the automatic placement of a combination of macro blocks and standard cells. Standard cells are partitioned into flexible virtual blocks during block placement and are later placed into the target area through an integrated optimization routine. Results for a number of examples are given, including those from standard placement benchmarks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
K. Ueda, H. Kitazawa, and I. Harada, "CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design," IEEE Trans. on Computer-Aided Design, pp. 12-22, 1985.
 
2
S. McNeary, R. Putamnda, H. Riflcin, R. Robilard, and D. Smith, "VITAL: A Cell-Based ASIC Assembler," VLSI Systems Design, vol. VII, no. 11, pp. 22-30, November 1986.
 
3
R. Putatunda, D. Smith, M. Stebnisky, C. Puschak, and P. Patent, "VITAL: Fully Automatic Placement Strategies for Very Large Semicustom Designs," International Conference on Computer Design, pp. 434-439, 1988.
 
4
D. Jepsen and C. Gelatt, "'Macro Placement by Monte Carlo Annealing," International Conference on Computer Design, p. 495, 1983.
 
5
 
6
 
7
S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by Simulated Annealing," Science, vol. 220, no. 4598, pp. 671-680, May 13, 1983.
 
8
S.R. White, "Concepts of Scale in Simulated Annealing," International Conference on Computer-Aided Design, pp. 646-651, 1984.
 
9
D.K. Ferry, "Interconnection Lengths and VLSI," IEEE Circuits and Devices Magazine, pp. 39-42, July 1985.
 
10
S. Hustin and A. Sangiovanni-Vincentelli, "Tim, a New Standard Cell Placement Program Based on the Simulated Annealing Algorithm," MCNC International Workshop on Placement and Routing, 1988.
 
11
M.D. Huang, F. Romeo, and A. Sangiovanni- Vincentelli, "'An Efficient Cooling Schedule for Simulated Annealing," international Conference on Computer-Aided Design, pp. 381-384, 1986.
 
12
C. Sechert and A. Sangiovanni-Vincentelli, "The Timberwolf Placement and Routing Package," IEEE Journal of Soild-State Circuits, vol. SC-20, no. 2, pp. 510-522, 1985.
 
13
C. Sechen, "'Macro-Cell Chip-Planning, Placement and Global Routing," in Vl~l Placement and Global Routing Using Simulated Annealing, pp. 93- 139, Kluwer Academic Publishers, 1988.
 
14
 
15
B. Eschermann, W. M. Dai, E. Kuh, and M. Pedram, "Hierarchical Placement for Macrocells: "A Meet in the Middle" Approach," International Conference on Computer-Aided Design, pp. 460- 463, 1988.


Collaborative Colleagues:
Michael Upton: colleagues
Khosrow Samii: colleagues
Stephen Sugiyama: colleagues

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