| Shared binary decision diagram with attributed edges for efficient Boolean function manipulation |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 27th ACM/IEEE conference on Design automation
table of contents
Orlando, Florida, United States
Pages: 52 - 57
Year of Publication: 1991
ISBN:0-89791-363-9
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Authors
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Shin-ichi Minato
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Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto, 606, Japan
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Nagisa Ishiura
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Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto, 606, Japan
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Shuzo Yajima
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Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto, 606, Japan
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Downloads (6 Weeks): 4, Downloads (12 Months): 37, Citation Count: 51
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ABSTRACT
The efficiency of Boolean function manipulation depends on the form of representation of Boolean functions. Binary Decision Diagrams (BDD's) are graph representations proposed by Akers and Bryant. BDD's have some properties which can be used to enable efficient Boolean function manipulation.
In this paper, we describe a technique of more efficient Boolean function manipulation that uses Shared Binary Decision Diagrams (SBDD's) with attributed edges. Our implements include an ordering algorithm of input variables and a method of handling don't care. We show experimental results produced by the implementation of the Boolean function manipulator.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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S. B. Akers: "Binary Decision Diagram", IEEE Trans. on Computers, Vol. C-27, No. 6, pp. 509- 516, (June, 1978).
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F. Brglez, H. Fujiwara: "A neutral netlist of 10 combinational circuits", Special Session on A TPG and Fault Simulation, Proc. 1985 IEEE International Symposium Circuit and Systems, Kyoto, Jap an, (June, 1985).
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M. Fujita, H. Fujisawa and N. Kawato: "Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams", IEEE ICCAD-88 Tech. Papers, pp. 2-5, (November, 1988).
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S. Malik, A. R. Wang, R. K. Brayton and A. S. Vimcentelli: "Logic Verification using Binary Decision Diagrams in a Logic Synthesis Environment" IEEE ICCAD-88 Tech. Papers, pp. 6-9, (November, 1988).
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CITED BY 51
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Hiroyuki Ochi , Koichi Yasuoka , Shuzo Yajima, Breadth-first manipulation of very large binary-decision diagrams, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.48-55, November 07-11, 1993, Santa Clara, California, United States
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Hiroyuki Ochi , Nagisa Ishiura , Shuzo Yajima, Breadth-first manipulation of SBDD of Boolean functions for vector processing, Proceedings of the 28th conference on ACM/IEEE design automation, p.413-416, June 17-22, 1991, San Francisco, California, United States
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Yutaka Deguchi , Nagisa Ishiura , Shuzo Yajima, Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits, Proceedings of the 28th conference on ACM/IEEE design automation, p.650-655, June 17-22, 1991, San Francisco, California, United States
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Hiroshige Fujii , Goichi Ootomo , Chikahiro Hori, Interleaving based variable ordering methods for ordered binary decision diagrams, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.38-41, November 07-11, 1993, Santa Clara, California, United States
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Nagisa Ishiura , Yutaka Deguchi , Shuzo Yajima, Coded time-symbolic simulation using shared binary decision diagram, Proceedings of the 27th ACM/IEEE conference on Design automation, p.130-135, June 24-27, 1990, Orlando, Florida, United States
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Zohair Sahraoui , Paul Six , Ivo Bolsens , Hugo De Man, Search space reduction through clustering in test generation, Proceedings of the conference on European design automation, p.242-247, September 18-22, 1995, Brighton, England
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Kuang-Chien Chen , Yusuke Matsunaga , Saburo Muroga , Masahiro Fujita, A resynthesis approach for network optimization, Proceedings of the 28th conference on ACM/IEEE design automation, p.458-463, June 17-22, 1991, San Francisco, California, United States
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K. Kubiak , S. Parkes , W. K. Fuchs , R. Saleh, Exact evaluation of diagnostic test resolution, Proceedings of the 29th ACM/IEEE conference on Design automation, p.347-352, June 08-12, 1992, Anaheim, California, United States
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H. Sawada , S. Yamashita , A. Nagoya, Restructuring logic representations with easily detectable simple disjunctive decompositions, Proceedings of the conference on Design, automation and test in Europe, p.755-761, February 23-26, 1998, Le Palais des Congrés de Paris, France
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Kenneth M. Butler , Don E. Ross , Rohit Kapur , M. Ray Mercer, Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams, Proceedings of the 28th conference on ACM/IEEE design automation, p.417-420, June 17-22, 1991, San Francisco, California, United States
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R. Drechsler , A. Sarabi , M. Theobald , B. Becker , M. A. Perkowski, Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams, Proceedings of the 31st annual conference on Design automation, p.415-419, June 06-10, 1994, San Diego, California, United States
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M. R. Mercer , R. Kapur , D. E. Ross, Functional approaches to generating orderings for efficient symbolic representations, Proceedings of the 29th ACM/IEEE conference on Design automation, p.624-627, June 08-12, 1992, Anaheim, California, United States
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Luc Burgun , N. Dictus , Alain Greiner , E. Prado Lopes , C. Sarwary, Multilevel logic optimization of very high complexity circuits, Proceedings of the conference on European design automation, p.14-19, September 19-23, 1994, Grenoble, France
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Pejman Lotfi-Kamran , Mohammad Hosseinabady , Hamid Shojaei , Mehran Massoumi , Zainalabedin Navabi, TED+: a data structure for microprocessor verification, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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