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Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 27th ACM/IEEE conference on Design automation table of contents
Orlando, Florida, United States
Pages: 52 - 57  
Year of Publication: 1991
ISBN:0-89791-363-9
Authors
Shin-ichi Minato  Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto, 606, Japan
Nagisa Ishiura  Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto, 606, Japan
Shuzo Yajima  Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto, 606, Japan
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 37,   Citation Count: 51
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ABSTRACT

The efficiency of Boolean function manipulation depends on the form of representation of Boolean functions. Binary Decision Diagrams (BDD's) are graph representations proposed by Akers and Bryant. BDD's have some properties which can be used to enable efficient Boolean function manipulation. In this paper, we describe a technique of more efficient Boolean function manipulation that uses Shared Binary Decision Diagrams (SBDD's) with attributed edges. Our implements include an ordering algorithm of input variables and a method of handling don't care. We show experimental results produced by the implementation of the Boolean function manipulator.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
S. B. Akers: "Binary Decision Diagram", IEEE Trans. on Computers, Vol. C-27, No. 6, pp. 509- 516, (June, 1978).
 
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5
F. Brglez, H. Fujiwara: "A neutral netlist of 10 combinational circuits", Special Session on A TPG and Fault Simulation, Proc. 1985 IEEE International Symposium Circuit and Systems, Kyoto, Jap an, (June, 1985).
 
6
M. Fujita, H. Fujisawa and N. Kawato: "Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams", IEEE ICCAD-88 Tech. Papers, pp. 2-5, (November, 1988).
 
7
S. Malik, A. R. Wang, R. K. Brayton and A. S. Vimcentelli: "Logic Verification using Binary Decision Diagrams in a Logic Synthesis Environment" IEEE ICCAD-88 Tech. Papers, pp. 6-9, (November, 1988).

CITED BY  51
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Collaborative Colleagues:
Shin-ichi Minato: colleagues
Nagisa Ishiura: colleagues
Shuzo Yajima: colleagues

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