Article

Early wire characterization for predictable network-on-chip global interconnects

Authors:

Ilhan Hatirnaz,

Stephane Badel,

Yusuf Leblebici,

Srinivasan Murali,

Giovanni De-MicheliAuthors Info & Claims

SLIP '07: Proceedings of the 2007 international workshop on System level interconnect prediction

Pages 57 - 64

https://doi.org/10.1145/1231956.1231969

Published: 17 March 2007 Publication History

Abstract

This work envisions a common design methodology, applicable for every interconnect level and based on early wire characterization, to provide a faster convergence to a feasible and robust design. We claim that such a novel design methodology is vital for upcoming nanometer technologies, where increased variations in both device characteristics and interconnect parameters introduce tedious design closure problems. The proposed methodology has been successfully applied to the wire synthesis of a Network-on-Chip interconnect to: (i) achieve a given delay and noise goals, and (ii) attain a more power-efficient design with respect to existing techniques.

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Cited By

Seidipiri RPatooghy AAfsharpour SFazeli M(2016)RASMAP: An efficient heuristic application mapping algorithm for network-on-chips2016 Eighth International Conference on Information and Knowledge Technology (IKT)10.1109/IKT.2016.7777757(149-155)Online publication date: Sep-2016
https://doi.org/10.1109/IKT.2016.7777757
Lan YLin HLo SHu YChen S(2011)A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable ChannelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.208693030:3(427-440)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1109/TCAD.2010.2086930
Paci GBertozzi DBenini L(2011)Variability compensation for full-swing against low-swing on-chip communicationIET Computers & Digital Techniques10.1049/iet-cdt.2009.01035:5(355)Online publication date: 2011
https://doi.org/10.1049/iet-cdt.2009.0103
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Index Terms

Early wire characterization for predictable network-on-chip global interconnects
1. Hardware
  1. Hardware validation

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Published In

cover image ACM Conferences

SLIP '07: Proceedings of the 2007 international workshop on System level interconnect prediction

March 2007

120 pages

ISBN:9781595936226

DOI:10.1145/1231956

General Chair:
Andrew Kennings
University of Waterloo, Canada
,
Program Chair:
Ion Mandoiu
University of Connecticut, USA

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 17 March 2007

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SLIP07

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SLIP07: International Workshop on System Level Interconnect Prediction

March 17 - 18, 2007

Texas, Austin, USA

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Cited By

Seidipiri RPatooghy AAfsharpour SFazeli M(2016)RASMAP: An efficient heuristic application mapping algorithm for network-on-chips2016 Eighth International Conference on Information and Knowledge Technology (IKT)10.1109/IKT.2016.7777757(149-155)Online publication date: Sep-2016
https://doi.org/10.1109/IKT.2016.7777757
Lan YLin HLo SHu YChen S(2011)A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable ChannelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.208693030:3(427-440)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1109/TCAD.2010.2086930
Paci GBertozzi DBenini L(2011)Variability compensation for full-swing against low-swing on-chip communicationIET Computers & Digital Techniques10.1049/iet-cdt.2009.01035:5(355)Online publication date: 2011
https://doi.org/10.1049/iet-cdt.2009.0103
Chen SLan YTsai WHu YChen SLan YTsai WHu Y(2011)Bidirectional Noc ArchitectureReconfigurable Networks-on-Chip10.1007/978-1-4419-9341-0_6(91-135)Online publication date: 15-Dec-2011
https://doi.org/10.1007/978-1-4419-9341-0_6
Ludovici DGaydadjiev GGilabert FGomez MBertozzi DPalesi MKumar SLu ZOgras U(2010)Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technologyProceedings of the Third International Workshop on Network on Chip Architectures10.1145/1921249.1921259(37-42)Online publication date: 4-Dec-2010
https://dl.acm.org/doi/10.1145/1921249.1921259
Paci GBertozzi DBenini LBenini LDe Micheli GAl-Hashimi BMueller W(2009)Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channelsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874959(1404-1409)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874959
Ludovici DGaydadjiev GBertozzi DBenini LLombardi FBhanja SMassoud YBahar R(2009)Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chipProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531574(125-128)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531574
Gilabert FLudovici DMedardoni SBertozzi DBenini LGaydadjiev G(2009)Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints2009 International Conference on Complex, Intelligent and Software Intensive Systems10.1109/CISIS.2009.30(681-687)Online publication date: Mar-2009
https://doi.org/10.1109/CISIS.2009.30
Gilabert FMedardoni SBertozzi DBenini LGomez MLopez PDuato J(2008)Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis FrameworkProceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip10.5555/1397757.1397991(107-116)Online publication date: 7-Apr-2008
https://dl.acm.org/doi/10.5555/1397757.1397991
Hatyrnaz IBadel SPazos NLeblebici Y(2007)Predictable system interconnects through accurate early wire characterization2007 IEEE International SOC Conference10.1109/SOCC.2007.4545476(287-290)Online publication date: Sep-2007
https://doi.org/10.1109/SOCC.2007.4545476

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