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The nuts and bolts of physical synthesis

Published: 17 March 2007 Publication History

Abstract

As technology scaling advances to the 45 and 32 nanometer nodes, more devices can fit onto a chip, which impliescontinued rapid design size growth. Naturally, it becomes increasingly challenging to achieve design closure on these enormous chips with tight performance and power constraints. Physical synthesis has emerged as a critical and powerful component of modern design methodologies to conquer such challenges. Starting from logic-level net list, physical synthesis creates a legally placed design while attempting to satisfy timing, power, and electrical constraints simultaneously. This paper briefly outlines the core components of physical synthesis timing closure and discusses some recent techniques that improve the solution quality and throughput of the physical synthesis process.

References

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L. Trevillyan, D. Kung, R. Ruri, L. N. Reddy, and M. A. Kazda, "An integrated environment for technology closure of deep-submicron ic designs," IEEE Design & Test of Computers, pp. 14--2, Jan. 2004.
[2]
C. J. Alpert, S. Karandikar, Z. Li, G.-J. Nam, S. T. Quay, H. Ren, C. N. Sze, P. G. Villarrubia, and M. Yildiz, "Techniques for fast physical synthesis," Proceedings of the IEEE, to appear 2007.
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S. K. Karandikar, C. J. Alpert, M.C. Yildiz, P. G. Villarrubia, S. T. Quay, and T. Mahmud, "Fast electrical correction using resizing and buffering," in Proc. Asia and South Pacific Design Automation Conf., 2007, to appear
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G.-J. Nam, S. Reda, C. Alpert, P. Villarrubia, and A. Kahng, "A fast hierarchical quadratic placement algorithm," IEEE Trans. on CAD of ICs and Systems, vol. 25, no. 4, April 2006.
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S. Hu, C. J. Alpert, J. Hu, S. K. Karandikar, Z. Li, W. Shi, and C. N. Sze, "Fast algorithms for slew constrained minimum cost buffering," in Proceedings of the ACM/IEEE Design Automation Conference, 2006, pp. 308--313.
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H. Ren, D. Z. Pan, C. J. Alpert, and P. Villarrubia, "Diffusion-based placement migration," in Proc. Design Automation Conf., 2005, pp. 515--520.

Cited By

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  • (2013)Intuitive ECO synthesis for high performance circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485529(1002-1007)Online publication date: 18-Mar-2013
  • (2010)Logical and physical restructuring of fan-in treesProceedings of the 19th international symposium on Physical design10.1145/1735023.1735046(67-74)Online publication date: 14-Mar-2010

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  1. The nuts and bolts of physical synthesis

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      cover image ACM Conferences
      SLIP '07: Proceedings of the 2007 international workshop on System level interconnect prediction
      March 2007
      120 pages
      ISBN:9781595936226
      DOI:10.1145/1231956
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 17 March 2007

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      View all
      • (2013)Intuitive ECO synthesis for high performance circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485529(1002-1007)Online publication date: 18-Mar-2013
      • (2010)Logical and physical restructuring of fan-in treesProceedings of the 19th international symposium on Physical design10.1145/1735023.1735046(67-74)Online publication date: 14-Mar-2010

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