skip to main content
10.1145/1231996.1232029acmconferencesArticle/Chapter ViewAbstractPublication PagesispdConference Proceedingsconference-collections
Article

ISPD placement contest updates and ISPD 2007 global routing contest

Published: 18 March 2007 Publication History

Abstract

In 2005 and 2006, ISPD successfully hosted two placement contests and released a total of 16 benchmark circuits. These benchmarks are all derived from real industrial circuits and present modern physical design challenges such as scalability, variety of floorplans, movable macro handling, and congestion mitigation. Since their release, the ISPD placement benchmarks have been extensively used by the physical design community. Indeed, we have observed significant progress in placement and floorplanning in the last few years. Much of this success can be credited to the fact that the placement community finally has large, well-defined benchmark circuits available that allow for fair comparisons among different algorithms. In this presentation, we report the most recent results on ISPD placement benchmarks and review how much progress each placement tool has achieved.
Continuing the tradition of spirited competition, ISPD 2007 presents a new contest in the global routing area. Similar to previous placement contests, a set of global routing benchmarks are released. These benchmarks are derived from the ISPD placement benchmark solutions; the level of complexity of these benchmarks is comparable to what real industry routing tools encounter. The global routing problem is formulated as a tile-based grid structure superimposed on the chip area; both 2D (single metal layer) and 3D (multiple metal layers) global routing instances will be released. The global routing solutions are evaluated on metrics such as total overflows, maximum overflow of a tile, routed wire length, and the number of vias. CPU time is not included this year to encourage high quality solutions. With placement and global routing benchmarks available, researchers in the fields of placement, floorplanning and global routing should have ample opportunities to attack realistic physical design challenges and contribute their solutions.
The placement and global routing contests have attracted strong entries from research groups around the world. In recognition of the importance of the problems, IEEE CEDA and SRC have donated prizes for the winners. Each year of the contest has brought unexpected twists and turns; we anticipate that this and future years will be no different.

Cited By

View all
  • (2022)Timing-Aware Layer Assignment for Advanced Process Technologies Considering via PillarsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310029641:6(1957-1970)Online publication date: Jun-2022
  • (2022)TritonRoute-WXL: The Open-Source Router With Integrated DRC EngineIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.307926841:4(1076-1089)Online publication date: Apr-2022
  • (2017)A Game Theory Based Post-Processing Method to Enhance VLSI Global RoutersIEEE Access10.1109/ACCESS.2017.26656015(1328-1339)Online publication date: 2017
  • Show More Cited By

Index Terms

  1. ISPD placement contest updates and ISPD 2007 global routing contest

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    ISPD '07: Proceedings of the 2007 international symposium on Physical design
    March 2007
    206 pages
    ISBN:9781595936134
    DOI:10.1145/1231996
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 18 March 2007

    Permissions

    Request permissions for this article.

    Check for updates

    Qualifiers

    • Article

    Conference

    ISPD07
    Sponsor:
    ISPD07: International Symposium on Physical Design
    March 18 - 21, 2007
    Texas, Austin, USA

    Acceptance Rates

    Overall Acceptance Rate 62 of 172 submissions, 36%

    Upcoming Conference

    ISPD '25
    International Symposium on Physical Design
    March 16 - 19, 2025
    Austin , TX , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)15
    • Downloads (Last 6 weeks)3
    Reflects downloads up to 15 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2022)Timing-Aware Layer Assignment for Advanced Process Technologies Considering via PillarsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310029641:6(1957-1970)Online publication date: Jun-2022
    • (2022)TritonRoute-WXL: The Open-Source Router With Integrated DRC EngineIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.307926841:4(1076-1089)Online publication date: Apr-2022
    • (2017)A Game Theory Based Post-Processing Method to Enhance VLSI Global RoutersIEEE Access10.1109/ACCESS.2017.26656015(1328-1339)Online publication date: 2017
    • (2016)Scaling Up Physical DesignProceedings of the 2016 on International Symposium on Physical Design10.1145/2872334.2872342(131-137)Online publication date: 3-Apr-2016
    • (2015)FuzzRouteACM Transactions on Design Automation of Electronic Systems10.1145/276712721:1(1-38)Online publication date: 2-Dec-2015
    • (2015)A Benchmark Suite to Jointly Consider Logic Synthesis and Physical DesignProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717785(185-192)Online publication date: 29-Mar-2015
    • (2015)Overhead for independent net approach for Global Routing2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2015.7250454(1-4)Online publication date: Feb-2015
    • (2014)Algorithms for Maze Routing With Exact Matching ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.227951633:1(101-112)Online publication date: 1-Jan-2014
    • (2013)Routing Challenges for Designs With Super High Pin DensityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.225646232:9(1357-1368)Online publication date: 1-Sep-2013
    • (2012)NCTU-GRIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.210278020:3(459-472)Online publication date: 1-Mar-2012
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media