Article

Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization

Authors:

Ashish K. Sing,

Michael OrshanskyAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 19 - 26

https://doi.org/10.1145/1233501.1233507

Published: 05 November 2006 Publication History

Abstract

Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable parameters. The two levels of tuning operate within a single variability budget, and because their effectiveness depends on the magnitude and the spatial structure of variability their joint co-optimization is required. In this paper we develop a formal optimization algorithm for such co-optimization and link it to the control and measurement overhead via the formal notions of measurement and control complexity.

We describe an optimization strategy that unifies design-time gate-level sizing and post-silicon adaptation using adaptive body bias at the chip level. The statistical formulation utilizes adjustable robust linear programming to derive the optimal policy for assigning body bias once the uncertain variables, such as gate length and threshold voltage, are known. Computational tractability is achieved by restricting optimal body bias selection policy to be an affine function of uncertain variables. We demonstrate good run-time and show that 5-35% savings in leakage power across the benchmark circuits are possible. Dependence of results on measurement and control complexity is studied and points of diminishing returns for both metrics are identified.

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Chenreddy ABandi NDelage EKoyejo SMohamed SAgarwal ABelgrave DCho KOh A(2022)Data-driven conditional robust optimizationProceedings of the 36th International Conference on Neural Information Processing Systems10.5555/3600270.3600962(9525-9537)Online publication date: 28-Nov-2022
https://dl.acm.org/doi/10.5555/3600270.3600962
IGAWA KYANAGISAWA MTOGAWA N(2017)A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation CompensationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E100.A.1439E100.A:7(1439-1451)Online publication date: 2017
https://doi.org/10.1587/transfun.E100.A.1439
Xu YWang BTeich J(2014)Parametric yield optimization using leakage-yield-driven floorplanning2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2014.6951860(1-6)Online publication date: Sep-2014
https://doi.org/10.1109/PATMOS.2014.6951860
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Index Terms

Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 November 2006

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ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Chenreddy ABandi NDelage EKoyejo SMohamed SAgarwal ABelgrave DCho KOh A(2022)Data-driven conditional robust optimizationProceedings of the 36th International Conference on Neural Information Processing Systems10.5555/3600270.3600962(9525-9537)Online publication date: 28-Nov-2022
https://dl.acm.org/doi/10.5555/3600270.3600962
IGAWA KYANAGISAWA MTOGAWA N(2017)A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation CompensationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E100.A.1439E100.A:7(1439-1451)Online publication date: 2017
https://doi.org/10.1587/transfun.E100.A.1439
Xu YWang BTeich J(2014)Parametric yield optimization using leakage-yield-driven floorplanning2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2014.6951860(1-6)Online publication date: Sep-2014
https://doi.org/10.1109/PATMOS.2014.6951860
Majzoobi MKong JKoushanfar F(2013)Low-power resource binding by postsilicon customizationACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244209718:2(1-22)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442097
Garg SMarculescu D(2012)System-level leakage variability mitigation for MPSoC platforms using body-bias islandsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217151220:12(2289-2301)Online publication date: 1-Dec-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2171512
Meijer MPineda de Gyvez J(2012)Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS CircuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.209197420:1(42-51)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1109/TVLSI.2010.2091974
Mostafa HAnis MElmasry M(2011)A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Die-to-Die and Within-Die Variations CompensationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.206050319:10(1848-1860)Online publication date: 1-Oct-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2060503
Brownell KKhan AWei GBrooks D(2011)Automating design of voltage interpolation to address process variationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203445719:3(383-396)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1109/TVLSI.2009.2034457
Zhang WLi XLiu FAcar ERutenbar RBlanton R(2011)Virtual ProbeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216453630:12(1814-1827)Online publication date: 1-Dec-2011
https://dl.acm.org/doi/10.1109/TCAD.2011.2164536
Zhuo CAgarwal KBlaauw DSylvester DScheffer LPhillips JHu A(2010)Active learning framework for post-silicon variation extraction and test cost reductionProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133538(508-515)Online publication date: 7-Nov-2010
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