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A gate delay model focusing on current fluctuation over wide-range of process and environmental variability

Published: 05 November 2006 Publication History

Abstract

This paper proposes a gate delay model that is suitable for timing analysis considering wide-range process and environmental variability. The proposed model focuses on current variation and its impact on delay is considered by replacing output load. The proposed model is applicable for large variability with current model constructed by DC analysis whose cost is small. The proposed model can also be used both in statistical static timing analysis and in conventional corner-based static timing analysis. Experimental results in a 90nm technology show that the gate delays of inverter, NAND and NOR are accurately estimated under gate length, threshold voltage, supply voltage and temperature fluctuation. We also verify that the proposed model can cope with slow input transition and RC output load. We demonstrate applicability to multiple-stage path delay and flip-flop delay, and show an application of sensitivity calculation for statistical timing analysis.

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Cited By

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  • (2013)Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply NoiseIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.223003521:12(2226-2239)Online publication date: 1-Dec-2013
  • (2012)On-chip measurement system for within-die delay variation of individual standard cells in 65-nm CMOSIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216225720:10(1876-1880)Online publication date: 1-Oct-2012
  • (2011)An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOSProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950846(109-110)Online publication date: 25-Jan-2011
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  1. A gate delay model focusing on current fluctuation over wide-range of process and environmental variability

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    cover image ACM Conferences
    ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
    November 2006
    147 pages
    ISBN:1595933891
    DOI:10.1145/1233501
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 05 November 2006

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    Author Tags

    1. gate delay model
    2. static timing analysis
    3. statistical timing analysis
    4. variability

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    View all
    • (2013)Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply NoiseIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.223003521:12(2226-2239)Online publication date: 1-Dec-2013
    • (2012)On-chip measurement system for within-die delay variation of individual standard cells in 65-nm CMOSIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216225720:10(1876-1880)Online publication date: 1-Oct-2012
    • (2011)An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOSProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950846(109-110)Online publication date: 25-Jan-2011
    • (2011)Voltage and Temperature-Aware SSTA Using Neural Network Delay ModelIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2011.216353224:4(533-544)Online publication date: Nov-2011
    • (2011)Overcoming carbon nanotube variations through co-optimized technology and circuit design2011 International Electron Devices Meeting10.1109/IEDM.2011.6131490(4.6.1-4.6.4)Online publication date: Dec-2011
    • (2009)Interconnect Modeling: A Physical Design PerspectiveIEEE Transactions on Electron Devices10.1109/TED.2009.202620856:9(1840-1851)Online publication date: Sep-2009
    • (2008)Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuitsProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509524(278-285)Online publication date: 10-Nov-2008
    • (2008)A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200609627:11(1983-1995)Online publication date: 1-Nov-2008

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