Article

From single core to multi-core: preparing for a new exponential

Authors:

Jeff Parkhurst,

John Darringer,

Bill GrundmannAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 67 - 72

https://doi.org/10.1145/1233501.1233516

Published: 05 November 2006 Publication History

Get Access

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

From single core to multi-core: preparing for a new exponential

Pages 67 - 72

Abstract
References

Abstract

In the past, processor design trends were dominated by increasingly complex feature sets, higher clock speeds, growing thermal envelopes and increasing power dissipation. Recently, clock speeds have tapered and thermal and power dissipation envelopes have remained flat. However, the demand for increasing performance continues which has fueled the move to integrated multiple processor (multi-core) designs. This paper discusses this trend towards multi-core processor designs, the design challenges that accompany it and a view of the research required to support it.

References

[1]

Gordon E. Moore, Cramming More Components onto Integrated Circuits. Electronics, April 19, 1965.

Google Scholar

[2]

Pham, D. et al. The Design and Implementation of a First-Generation CELL Processor. In ISSCC Digest of Technical Papers. (San Francisco, CA, USA, Feb 6-10, 2005) p. 184--5

Google Scholar

[3]

Charlie Johnson, Jeff Welser, Future processors: flexible and modular. In Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19--21, 2005, 4--6

Digital Library

Google Scholar

[4]

http://ramp.eecs.berkeley.edu/

Google Scholar

[5]

http://www.itrs.net/

Google Scholar

[6]

J. Cong, A. Jagannathan, G. Reinman, and M. Romesis, "Microarchitecture Evaluation With Physical Planning," in Design Automation Conference, pp. 32--35, June 2003.

Digital Library

Google Scholar

[7]

J. Cong, A. Jagannathan, K. Konigsfeld, D. Milliron, M. Mohan, G. Reinman, M. Romesis, and H. Yang, "Micro-Architecture Evaluation and Optimization with Interconnect Pipelining," Proceedings of the Asia South Pacific Design Automation Conference, pp. 8--15, January 2005.

Digital Library

Google Scholar

[8]

J. Cong, A. Jagannathan, Y. Ma, G. Reinman and J. Wei, "An Automated Design Flow for 3D Microarchitecture Evaluation," Proceedings of the 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006), Yokohama, Japan, pp.384--389, January 2006.

Digital Library

Google Scholar

[9]

S. S. Sapatnekar, Y. Zhan, and T. Zhang, "Temperature-Aware Routing in 3D ICs," Proceedings of the Asia-South Pacific Design Automation Conference, pp. 309--314, 2006.

Digital Library

Google Scholar

[10]

http://www.spiritconsortium.com/

Google Scholar

[11]

http://www.systemc.org/

Google Scholar

[12]

http://www.si2.org/?page=69

Google Scholar

[13]

R. Bergamaschi, S. Bhattacharya, D. Brand, J. Darringer, A. Herkersdorf, J. Morrell, I. Nair, P. Sagmeister, and Y. Shin, "Early Analysis Tools for System-on-a-Chip Design", IBM Journal of Research and Development, v.46, no.6, 691--707, November 2001.

Digital Library

Google Scholar

[14]

Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, John A. Darringer, Nagu R. Dhanwada, William E. Dougherty, Indira Nair, Sarala Paliwal, and Youngsoo Shin: SEAS: a system for early analysis of SoCs. CODES+ISSS, 150--155, 2003.

Digital Library

Google Scholar

Cited By

View all

Lenke OPetri RWild THerkersdorf A(2021)PEPERONI: Pre-Estimating the Performance of Near-Memory IntegrationProceedings of the International Symposium on Memory Systems10.1145/3488423.3519329(1-6)Online publication date: 27-Sep-2021
https://dl.acm.org/doi/10.1145/3488423.3519329
Rheindt SSabirov TLenke OWild THerkersdorf A(2020)X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer ArchitecturesProceedings of the International Symposium on Memory Systems10.1145/3422575.3422792(178-193)Online publication date: 28-Sep-2020
https://dl.acm.org/doi/10.1145/3422575.3422792
Abadi MKeidar-Barner SPidan DVeksler T(2019)Verifying Parallel Code After Refactoring Using Equivalence CheckingInternational Journal of Parallel Programming10.1007/s10766-017-0548-447:1(59-73)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1007/s10766-017-0548-4
Show More Cited By

Index Terms

From single core to multi-core: preparing for a new exponential
1. Hardware
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language features
        Control structures

Recommendations

Hybrid multi-core architecture for boosting single-threaded performance

The scaling of technology and the diminishing return of complicated uniprocessors have driven the industry towards multicore processors. While multithreaded applications can naturally leverage the enhanced throughput of multi-core processors, a large ...
Enabling SIMT Execution Model on Homogeneous Multi-Core System

Single-instruction multiple-thread (SIMT) machine emerges as a primary computing device in high-perfor-mance computing, since the SIMT execution paradigm can exploit data-level parallelism effectively. This article explores the SIMT execution potential ...
Performance analysis of multi-threaded multi-core CPUs
MES '13: Proceedings of the First International Workshop on Many-core Embedded Systems

Processors are constantly changing and becoming more advanced. They incorporate new concepts and ideas into the architecture with each evolution. One such concept is multi-threading. It aims at increasing the processors performance by reducing its idle ...

Comments

Information & Contributors

Information

Published In

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2006

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ICCAD06

Sponsor:

SIGDA
IEEE-CAS
IEEE-CS

ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

27
Total Citations
View Citations
1,470
Total Downloads

Downloads (Last 12 months)26
Downloads (Last 6 weeks)7

Reflects downloads up to 07 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Lenke OPetri RWild THerkersdorf A(2021)PEPERONI: Pre-Estimating the Performance of Near-Memory IntegrationProceedings of the International Symposium on Memory Systems10.1145/3488423.3519329(1-6)Online publication date: 27-Sep-2021
https://dl.acm.org/doi/10.1145/3488423.3519329
Rheindt SSabirov TLenke OWild THerkersdorf A(2020)X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer ArchitecturesProceedings of the International Symposium on Memory Systems10.1145/3422575.3422792(178-193)Online publication date: 28-Sep-2020
https://dl.acm.org/doi/10.1145/3422575.3422792
Abadi MKeidar-Barner SPidan DVeksler T(2019)Verifying Parallel Code After Refactoring Using Equivalence CheckingInternational Journal of Parallel Programming10.1007/s10766-017-0548-447:1(59-73)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1007/s10766-017-0548-4
Surakhi OKhanafseh MSarhan S(2018)A Survey on Parallel Multicore Computing: Performance & ImprovementAdvances in Science, Technology and Engineering Systems Journal10.25046/aj0303213:3(152-160)Online publication date: Jun-2018
https://doi.org/10.25046/aj030321
Zhao HZheng FWu JNan BLi BMei KEmrouznejad AQian Z(2018)Automatic Parallelization for Binary on Multi-core PlatformsProceedings of the 2nd International Conference on Computer Science and Application Engineering10.1145/3207677.3277982(1-6)Online publication date: 22-Oct-2018
https://dl.acm.org/doi/10.1145/3207677.3277982
Bhowmik SPradhan SBhattacharyya B(2018)Power Supply Noise Reduction of Multicore CPU by Staggering Current and Variable Clock FrequencyIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2018.28031398:5(875-882)Online publication date: May-2018
https://doi.org/10.1109/TCPMT.2018.2803139
Kim SChung J(2017)Synthesis of activation-parallel convolution structures for neuromorphic architecturesProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130773(1689-1694)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130773
Ansari DKim K(2017)Performance Analysis of Double-Layer Microchannel Heat Sinks under Non-Uniform Heating Conditions with Random HotspotsMicromachines10.3390/mi80200548:2(54)Online publication date: 14-Feb-2017
https://doi.org/10.3390/mi8020054
Kim SChung J(2017)Synthesis of activation-parallel convolution structures for neuromorphic architecturesDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927265(1685-1690)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927265
Baroudi TSeghir RLoechner V(2017)Optimization of Triangular and Banded Matrix Operations Using 2d-Packed LayoutsACM Transactions on Architecture and Code Optimization10.1145/316201614:4(1-19)Online publication date: 18-Dec-2017
https://dl.acm.org/doi/10.1145/3162016
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Hybrid multi-core architecture for boosting single-threaded performance

Enabling SIMT Execution Model on Homogeneous Multi-Core System

Performance analysis of multi-threaded multi-core CPUs

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations