On bounding the delay of a critical path
Authors: 
Leonard Lee, Li-C. WangAuthors Info & Claims
Leonard Lee, Li-C. WangAuthors Info & ClaimsPages 81 - 88
Abstract
Process variations cause different behavior of timing-dependent effects across different chips. In this work, we analyze one example of timing-dependent effects, cross-coupling capacitance, and the complex problem space created by considering coupling and process variations together. The delay of a critical path under these conditions is difficult to bound for design and test. We develop a methodology that analyzes this complex space by decomposing the problem space along three dimensions: the aggressor space, test space, and sample space. For design, we utilize an OBDD-based approach to prune the aggressor space based on logical constraints, which can be combined with a worst-case timing window simulator to prune based on both logical and timing constraints. After pruning, the reduced aggressor space can be used to derive a more accurate timing bound. Solving the problems in the test and sample spaces is postponed to the post-silicon stage, where we propose a test selection methodology for bounding the delay of every sample. This methodology is based on probability density estimation and has a tradeoff between the number of tests to apply and the tightness of the delay bound obtained. Experimental results based on benchmark examples are presented to show the effectiveness of the proposed methodology.
References
[1]
Layout and parasitic information for ISCAS circuits. http://dropzone.tamu.edu/~xiang/iscas.html.
[2]
The R project for statistical computing. http://www.r-project.org/.
[3]
A. Agarwal et al. Statistical gate delay model considering multiple input switching. In Design Automation Conf., pages 658--663, June 2004.
[4]
R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Trans. Comput., 35(8):677--691, 1986.
[5]
V. Chandramouli and K. A. Sakallah. Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time. In Design Automation Conf., pages 617--622, June 1996.
[6]
T. S. Chang et al. Test generation for maximizing ground bounce for internal circuitry with recovergent fan-outs. In VLSI Test Symp., pages 358--366, 2001.
[7]
P. Chen et al. Miller factor for gate-level coupling delay calculation. In ICCAD, pages 68--74, Nov. 2000.
[8]
W. Chen et al. Test generation in VLSI circuits for crosstalk noise. In ITC, pages 641--650, 1998.
[9]
W. Chen et al. Test generation for crosstalk-induced delay in integrated circuits. In ITC, page 191, 1999.
[10]
F. Dartu and L. T. Pileggi. Calculating worst-case gate delays due to dominant capacitance coupling. In Design Automation Conf., pages 46--51, 1997.
[11]
Y.-M. Jiang and K.-T. Cheng. Vector generation for power supply noise estimation and verification of deep submicron designs. IEEE Trans. VLSI Syst., 9(2):329--340, Apr. 2001.
[12]
Y.-M. Jiang et al. Estimation for maximum instantaneous current through supply lines for CMOS circuits. Tran. VLSI Syst., 8(1):61--73, Feb. 2000.
[13]
A. B. Kahng et al. Noise and delay uncertainty studies for coupled RC interconnects. In ASIC/SOC, 1999.
[14]
A. Krstic et al. Delay testing considering power supply noise effects. In ITC, pages 181--190, 1999.
[15]
A. Krstic et al. Delay testing considering crosstalk-induced effects. In ITC, page 558, Oct. 2001.
[16]
L. Lee et al. On generating tests to cover diverse worst-case timing corners. In Intl. Symp. on Defect and Fault Tolerance in VLSI, pages 415--423, 2005.
[17]
L. Lee et al. On silicon-based speed path identification. In VLSI Test Symposium, pages 35--41, May 2005.
[18]
F. Lu et al. A circuit SAT solver with signal correlation guided learning. In DATE, page 892, 2003.
[19]
J. Qian et al. Modeling the effective capacitance for the RC interconnect of CMOS gates. IEEE Trans. Computer-Aided Design, 13(12):1526--1555, Dec. 1994.
[20]
T. Sakurai. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's. Trans. Elect. Dev., 40(1):118--124, Jan. 1993.
[21]
S. J. Sheather and M. C. Jones. A reliable data-based bandwidth selection method for kernel density estimation. J. Roy. Statist. Soc. B, 53:683--690, 1991.
[22]
B. W. Silverman. Density Estimation. Chapman and Hall, 1986.
[23]
V. N. Vapnik. The Nature of Statistical Learning Theory. Springer, 2nd edition, 1999.
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- On bounding the delay of a critical path
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Published: 05 November 2006
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ICCAD06: The International Conference on Computer-Aided Design 2006
November 5 - 9, 2006
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