Handling inductance in early power grid verification

As part of integrated circuit design verification, one should check if the voltage drop on the power grid exceeds some critical threshold. One way to do this is by simulation, but that is computationally expensive and gets prohibitive for large circuits with a large variety of possible operational modes. Another limitation of a simulation-based approach is that it requires complete knowledge of the logic circuitry drawing current from the grid, thus precluding grid verification early in the design process. In this paper, we model the grid as an RLC circuit and we propose three verification techniques that can be applied in the early stages of the design process. These techniques do not require exact knowledge of the circuit currents. Instead, the currents drawn by the logic beneath the power grid are described by means of current constraints that capture the uncertainty about circuit details and activity. The first verification approach gives the exact worst-case voltage drop at every node of the grid, but it is slow. A second faster approach gives conservative bounds on the worst-case voltage drop at every node of the grid. The third approach is much faster; it is a conservative approach which simply checks if the grid voltage drop exceeds some pre-defined thresholds, without actually computing the worst-case voltage drop at every node.