Article

Testing delay faults in asynchronous handshake circuits

Authors:

Yiorgos MakrisAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 193 - 197

https://doi.org/10.1145/1233501.1233540

Published: 05 November 2006 Publication History

Abstract

As a class of asynchronous circuits, handshake circuits are designed to tolerate variation of gate delays. However, certain timing constraints, such as the bundled data assumption, are exploited in the single-rail implementation of these circuits in order to simplify them. Therefore, any delay fault in the circuit may cause one of two problems, namely performance degradation or logic errors. To address the challenges incurred by the autonomous behavior of handshake circuits during at-speed test, we propose test methods for both types of delay faults based on a DFT strategy which greatly simplifies the complexity of test generation. The efficiency of the proposed methodology is demonstrated through experimental results on several handshake circuits.

References

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G. Gill, A. Agiwal, M. Singh, F. Shi, and Y. Makris. Low overhead testing of delay faults in high-speed asynchronous pipelines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 46--56, 2006.

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Cited By

Jayanthy SBhuvaneswari MJayanthy SBhuvaneswari M(2018)Simulation Based Test Generation for Crosstalk Delay Faults in Asynchronous Sequential CircuitsTest Generation of Crosstalk Delay Faults in VLSI Circuits10.1007/978-981-13-2493-2_9(141-150)Online publication date: 21-Sep-2018
https://doi.org/10.1007/978-981-13-2493-2_9
Jayanthy SBhuvaneswari MJayanthy SBhuvaneswari M(2018)Test Generation Algorithms for Crosstalk FaultsTest Generation of Crosstalk Delay Faults in VLSI Circuits10.1007/978-981-13-2493-2_3(37-55)Online publication date: 21-Sep-2018
https://doi.org/10.1007/978-981-13-2493-2_3
JAYANTHY SBHUVANESWARI M(2015)Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuitsSadhana10.1007/s12046-014-0302-140:1(107-119)Online publication date: 23-Jan-2015
https://doi.org/10.1007/s12046-014-0302-1
Show More Cited By

Index Terms

Testing delay faults in asynchronous handshake circuits
1. Hardware
  1. Hardware test
  2. Robustness
    1. Hardware reliability

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cover image ACM Conferences

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2006

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ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Jayanthy SBhuvaneswari MJayanthy SBhuvaneswari M(2018)Simulation Based Test Generation for Crosstalk Delay Faults in Asynchronous Sequential CircuitsTest Generation of Crosstalk Delay Faults in VLSI Circuits10.1007/978-981-13-2493-2_9(141-150)Online publication date: 21-Sep-2018
https://doi.org/10.1007/978-981-13-2493-2_9
Jayanthy SBhuvaneswari MJayanthy SBhuvaneswari M(2018)Test Generation Algorithms for Crosstalk FaultsTest Generation of Crosstalk Delay Faults in VLSI Circuits10.1007/978-981-13-2493-2_3(37-55)Online publication date: 21-Sep-2018
https://doi.org/10.1007/978-981-13-2493-2_3
JAYANTHY SBHUVANESWARI M(2015)Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuitsSadhana10.1007/s12046-014-0302-140:1(107-119)Online publication date: 23-Jan-2015
https://doi.org/10.1007/s12046-014-0302-1
Dobai RGramatová E(2011)A novel automatic test pattern generator for asynchronous sequential digital circuitsMicroelectronics Journal10.1016/j.mejo.2010.10.01342:3(501-508)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1016/j.mejo.2010.10.013

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