Article

Design and CAD challenges in 45nm CMOS and beyond

Authors:

David J. Frank,

Dorel TomaAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 329 - 333

https://doi.org/10.1145/1233501.1233567

Published: 05 November 2006 Publication History

Abstract

With semiconductor industry's aggressive march towards 45nm CMOS technology and introduction of new materials and device structures in sight for 32nm and 22nm nodes, it is crucial for the IC design and CAD community to understand the challenges posed by these potential technology changes. This tutorial will focus on these challenges starting from front end of line (devices) to the back end of line (interconnects) and finally the impact on CAD. We will discuss the impact of various device technology options/improvements, such as high-k, metal gate, low temperature operation, increased mobility and reduced variability, on the overall chip performance in the context of power-constrained technology optimization. This will show that power constraints limit, but do not eliminate, the performance improvements available from new technology. The integration issues related to low-k materials for interconnects in 45nm and beyond will be examined in the context of advanced IC design. Ultra low-k materials, evolution of etch and chemical mechanical polishing (CMP), and techniques to limit damage during processing and their impact on design performance will be discussed in detail. These advanced device and interconnect structures and materials including 3D technology have tremendous impact on the direction of the CAD industry. We will discuss the design methodology and CAD implications of these imminent technology changes.

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Cited By

Zhang JYuan FYe RXu QHenkel J(2013)ForTERProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561839(55-60)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561839
Yuan FXu Q(2013)InTimeFixProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488959(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488959
Yuan FLiu YJone WXu Q(2013)On testing timing-speculative circuitsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488771(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488771
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Index Terms

Design and CAD challenges in 45nm CMOS and beyond
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2006

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ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Zhang JYuan FYe RXu QHenkel J(2013)ForTERProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561839(55-60)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561839
Yuan FXu Q(2013)InTimeFixProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488959(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488959
Yuan FLiu YJone WXu Q(2013)On testing timing-speculative circuitsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488771(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488771
Zhang JYuan FYe RXu Q(2013)ForTER: A forward error correction scheme for timing error resilience2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2013.6691097(55-60)Online publication date: Nov-2013
https://doi.org/10.1109/ICCAD.2013.6691097
Liu YYe RYuan FXu Q(2013)Optimization for timing-speculated circuits by redundancy addition and removal2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)10.1109/ETS.2013.6569376(1-6)Online publication date: May-2013
https://doi.org/10.1109/ETS.2013.6569376
Liu YYe RYuan FKumar RXu QHu A(2012)On logic synthesis for timing speculationProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429512(591-596)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429512
Liu YYuan FXu QStok LDutt NHassoun S(2011)Re-synthesis for cost-efficient circuit-level timing speculationProceedings of the 48th Design Automation Conference10.1145/2024724.2024760(158-163)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024760
Sinha SSuh JBakkaloglu BCao Y(2011)Workload-Aware Neuromorphic Design of the Power ControllerIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2011.21652331:3(381-390)Online publication date: Sep-2011
https://doi.org/10.1109/JETCAS.2011.2165233
Sinha SSuh JBakkaloglu BCao Y(2011)A workload-aware neuromorphic controller for dynamic power and thermal management2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)10.1109/AHS.2011.5963936(200-207)Online publication date: Jun-2011
https://doi.org/10.1109/AHS.2011.5963936
Zhuo CChang YSylvester DBlaauw DLin Y(2010)Design time body bias selection for parametric yield improvementProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899880(681-688)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899880
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