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Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts

Published: 05 November 2006 Publication History

Abstract

Parasitic effects are extremely significant for the performance of analog and RF integrated circuits. Although layout retargeting for technology migration or specification update is able to preserve designers' intent, the associated layout parasitics cannot be guaranteed to meet the performance requirements. In this paper, we present a novel algorithm that performs parasitic-aware automatic layout retargeting for analog/RF integrated circuits. Given parasitic resistance/capacitance bounds and matching constraints ensuring desired circuit performance, the algorithm creates a reduced-template-graph from original layouts and adds parasitic constraints. Using a two-dimensional hybrid scheme of graph-based optimization and nonlinear programming, the nonlinear problem is solved effectively and efficiently. The algorithm has successfully retargeted operational amplifiers and an RF low-noise amplifier within minutes of CPU time.

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Cited By

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  • (2024)Performance-Driven Analog Layout Automation: Current Status and Future DirectionsProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
  • (2023)Generating the Generator: A User-Driven and Template-Based Approach towards Analog Layout AutomationElectronics10.3390/electronics1204104712:4(1047)Online publication date: 20-Feb-2023
  • (2014)Optimization models in layout2014 9th Iberian Conference on Information Systems and Technologies (CISTI)10.1109/CISTI.2014.6876978(1-6)Online publication date: Jun-2014
  • Show More Cited By

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  1. Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts

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    cover image ACM Conferences
    ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
    November 2006
    147 pages
    ISBN:1595933891
    DOI:10.1145/1233501
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 05 November 2006

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    Author Tags

    1. analog/RF integrated circuits
    2. design reuse
    3. layout automation
    4. layout symmetry
    5. parasitics

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    View all
    • (2024)Performance-Driven Analog Layout Automation: Current Status and Future DirectionsProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
    • (2023)Generating the Generator: A User-Driven and Template-Based Approach towards Analog Layout AutomationElectronics10.3390/electronics1204104712:4(1047)Online publication date: 20-Feb-2023
    • (2014)Optimization models in layout2014 9th Iberian Conference on Information Systems and Technologies (CISTI)10.1109/CISTI.2014.6876978(1-6)Online publication date: Jun-2014
    • (2008)An Integrated Layout-Synthesis Approach for Analog ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.92341727:7(1179-1189)Online publication date: 1-Jul-2008
    • (2008)Parasitic-Aware Optimization and Retargeting of Analog LayoutsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.91759427:5(791-802)Online publication date: 1-May-2008

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