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Analog placement with symmetry and other placement constraints

Published: 05 November 2006 Publication History

Abstract

In order to handle device matching in analog circuits, some pairs of modules are required to be placed symmetrically. This paper addresses this device-level placement problem for analog circuits and our approach can handle symmetry constraint and other placement constraints simultaneously. The problem of placing devices with symmetry constraint has been extensively studied but none of the previous works has considered symmetry constraint with other placement constraints simultaneously. Instead of handling the constraints by having a penalty term in the cost function to penalize violations, a unified method is proposed that, by adjusting the edge weights in a pair of constraint graphs, can try to satisfy all the placement and symmetry constraints simultaneously in a candidate floorplan solution. The maximum distance of the modules in a symmetry group from the corresponding symmetry axis will be minimized in this weight adjusting step, in order to minimize the total packing area. We have compared our method with the most updated results on this problem [2] when there are only symmetry constraints and results show that our approach can give solutions of better quality, in an acceptable amount of run time. We will also demonstrate the effectiveness of our approach in handling different types of constraints simultaneously by testing on data sets with both symmetry and other placement constraints, and the results are very promising.

References

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F. Balasa and K. Lampaert. Symmetry within the Sequence-Pair Representation in the Context of Placement for Analog Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(7):712--731, 2000.
[2]
F. Balasa, S. C. Maruvada, and K. Krishnamoorthy. On the Exploration of the Solution Space in Analog Placement with Symmetry Constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(2):177--191, 2004.
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Y. C. Chang, Y. W. Chang, G. M. Wu, and S. W. Wu. B*-Trees: A New Representation for Non-Slicing Floorplans. Proceedings of the 37th ACM/IEEE Design Automation Conference, 2000.
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Pei-Ning Guo, Chung-Kuan Cheng, and Takeshi Yoshimura. An O-Tree Representation of Non-Slicing Floorplan and Its Applications. Proceedings of the 36th ACM/IEEE Design Automation Conference, pages 268--273, 1999.
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Shinichi Kouda, Chikaaki Kodama, and Kunihiro Fujiyoshi. Improved Method of Cell Placement with Symmetry Constraints for Analog IC Layout Design. International Symposium on Physical Design, pages 192--199, 2006.
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K. Lampaert, G. Gielen, and W. Sansen. A Performance-driven Placement Tool for Analog Integrated Circuits. IEEE J. Solid-State Circuits, 30(7):773--780, 1995.
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J. M. Lin and Y. W. Chang. TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(6), 2004.
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Y. X. Pang, F. Balasa, K. Lampaert, and C. K. Cheng. Block Placement with Symmetry Constraints based on the O-tree Nonslicing Representation. Proceedings of the 37th ACM/IEEE Design Automation Conference, pages 464--467, 2000.
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G. M. Wu, J. M. Lin, Y. W. Chang, and R. H. Chuang. Placement with Symmetry Constraints for Analog Layout Design. IEEE Asia and South Pacific Design Automation Conference, pages 1135--1138, 2005.
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Evangeline F. Y. Young, Chris C. N. Chu, and M. L. Ho. Placement Constraints in Floorplan Design. IEEE Transactions on Very Large Scale Integration Systems, 12(7):735--745, 2004.

Cited By

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  • (2018)Routable and Matched Layout Styles for Analog Module GenerationACM Transactions on Design Automation of Electronic Systems10.1145/318216923:4(1-17)Online publication date: 28-Jun-2018
  • (2016)Pareto front analog layout placement using satisfiability modulo theoriesProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972136(1411-1416)Online publication date: 14-Mar-2016
  • (2016)QB-treesProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898074(1-6)Online publication date: 5-Jun-2016
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cover image ACM Conferences
ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
November 2006
147 pages
ISBN:1595933891
DOI:10.1145/1233501
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 05 November 2006

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Author Tags

  1. analog circuits
  2. placement
  3. sequence-pair
  4. symmetry constraints

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Cited By

View all
  • (2018)Routable and Matched Layout Styles for Analog Module GenerationACM Transactions on Design Automation of Electronic Systems10.1145/318216923:4(1-17)Online publication date: 28-Jun-2018
  • (2016)Pareto front analog layout placement using satisfiability modulo theoriesProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972136(1411-1416)Online publication date: 14-Mar-2016
  • (2016)QB-treesProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898074(1-6)Online publication date: 5-Jun-2016
  • (2015)Beyond GORDIAN and KraftwerkProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2723571(133-140)Online publication date: 29-Mar-2015
  • (2014)An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size DesignsACM Transactions on Design Automation of Electronic Systems10.1145/261176119:3(1-25)Online publication date: 23-Jun-2014
  • (2014)An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programmingTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test10.1109/VLSI-DAT.2014.6834871(1-4)Online publication date: Apr-2014
  • (2013)Automatic placement for matched devices of analog circuits2013 Ninth International Conference on Natural Computation (ICNC)10.1109/ICNC.2013.6818260(1723-1727)Online publication date: Jul-2013
  • (2012)Routability-driven placement algorithm for analog integrated circuitsProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160934(71-78)Online publication date: 25-Mar-2012
  • (2012)Challenges and solutions in modern analog placementProceedings of Technical Program of 2012 VLSI Design, Automation and Test10.1109/VLSI-DAT.2012.6212641(1-4)Online publication date: Apr-2012
  • (2011)A corner stitching compliant B*-tree representation and its applications to analog placementProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132444(507-511)Online publication date: 7-Nov-2011
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