Article

A timing dependent power estimation framework considering coupling

Authors:

DiaaEldin Khalil,

Hai ZhouAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 401 - 407

https://doi.org/10.1145/1233501.1233582

Published: 05 November 2006 Publication History

Abstract

In this paper, we propose a timing dependent dynamic power estimation framework that considers the impact of coupling and glitches. We show that relative switching activities and times of coupled nets significantly affect dynamic power consumption, and neither should be ignored during power estimation. To capture the timing dependence, an approach to efficient representation and propagation of switching-window distributions through a circuit, considering coupling induced delay variations, is developed. Based on the propagated switchingwindow distributions, power consumption in charging or discharging coupling capacitances is calculated, and accounted for in the total power. Experimental results for the ISCAS'85 benchmarks demonstrate that ignoring the impact of timing dependent coupling on power can cause up to 59% error in coupling power estimation (up to 25% error in total power estimation).

References

[1]

D. W. Dobberpuhl et al., "A 200Mhz, 64bit dual-issue CMOS microprocessor," in IEEE Journal of Solid State Circuits, Vol 27(11), 1992, pp. 1555--1564.

[2]

D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," in IEEE Journal of Solid State Circuits, Vol 29, 1994, pp. 663--670.

[3]

R. Mehra, L. M. Guerra, and J. M. Rabaey, "A partitioning scheme for optimizing interconnect power," in IEEE Journal of Solid State Circuits, Vol 32, 1997, pp. 433--443.

[4]

E. D. Man and M. Schobinger, "Power dissipation in the clock system of highly pipelined ULSI CMOS circuits," in Proc. International Workshop on Low Power Design, 1994, pp. 133--138.

[5]

J. Pangjun and S. Sapatnekar, "Low power clock distribution using multiple voltages and reduced swings," in IEEE Transactions on Very Large Scale Integration Systems, Vol 10, 2002, pp. 309--318.

Digital Library

[6]

P. Gupta and A. B. Kahng, "Quantifying error in dynamic power estimation of CMOS circuits," in Proc. Intl. Symposium on Quality Electronic Design, 2003, pp. 273--278.

Digital Library

[7]

S. C. Wong, G. Y. Lee, and D. J. Ma, "Modeling of interconnect capacitance, delay and crosstalk in VLSI," in IEEE Transactions on Semiconductor Manufacturing, Vol 13, 2000, pp. 108--111.

[8]

Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," in Proc. Custom Integrated and Circuits Conference, 2000, pp. 201--204.

[9]

Nanoscale Integration and Modeling Group at ASU, Predictive technology models. http://www.eas.asu.edu/~ptm/.

[10]

M. Ghoneima and Y. Ismail, "Effect of relative delay on the dissipated energy in coupled interconnects," in Proc. Intl. Symposium on Circuits and Systems, 2004, pp. 525--528.

[11]

S. M. Kang, "Accurate simulation of power dissipation in VLSI circuits," in IEEE Journal of Solid State Circuits, Vol 21(5), 1986, pp. 889--891.

[12]

M. A. Cirit, "Estimating dynamic power consumption of CMOS circuits," in Proc. Intl. Conf. on Computer-Aided Design, 1987, pp. 534--537.

[13]

F. Najm, R. Burch, P. Yang, and I. Hajj, "Probabilistic simulation for reliability analysis of CMOS VLSI circuits," in IEEE Transactions on Computer Aided Design, 1990, pp. 439--450.

Digital Library

[14]

G. I. Stamoulis and I. N. Hajj, "Improved techniques for probabilistic simulation including signal correlation effects," in Proc. of the Design Automation Conf., 1993, pp. 379--383.

Digital Library

[15]

C. Y. Tsui, M. Pedram, and A. M. Despain, "Efficient estimation of dynamic power consumption under a real delay model," in Proc. Intl. Conf. on Computer-Aided Design, 1993, pp. 224--228.

Digital Library

[16]

T. Uchino and J. Cong, "An interconnect energy model considering coupling effects," in Proc. of the Design Automation Conf., 2001, pp. 555--558.

Digital Library

[17]

A. Ghosh, S. Devdas, K. Keutzer, and J. White, "Estimation of average switching activity in combinational and sequential circuits," in Proc. of the Design Automation Conf., 1992, pp. 253--259.

Digital Library

[18]

M. Xakellis and F. Najm, "Statistical estimation of the switching activity in digital circuits," in Proc. of the Design Automation Conf., 1994, pp. 728--733.

Digital Library

[19]

H. Zhou, "Timing analysis with crosstalk is a fixpoint on a complete lattice," in IEEE Transactions on Computer-Aided Design, September 2003, pp. 1261--1269.

Digital Library

[20]

P. Chen, Y. Kukimoto, C. C. Teng, and K. Keutzer, "On convergence of switching window computation in presence of crosstalk noise," in International Symposium on Physical Design, 2002, pp. 84--89.

Digital Library

[21]

S. S. Sapatnekar, "A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing," IEEE Transactions on Computer Aided Design, 2000.

Digital Library

[22]

F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinatorial benchmark circuits," in Proc. Intl. Symposium on Circuits and Systems, 1985, pp. 695--698.

[23]

A. Agarwal, K. Chopra, and D. Blaauw, "Statistical timing based optimization using gate sizing," in Proc. DATE: Design Automation and Test in Europe, 2005, pp. 400--405.

Digital Library

[24]

P. Chen, Y. Kukimoto, and K. Keutzer, "Refining switching window by time slots for crosstalk noise calculation," in Proc. Intl. Conf. on Computer-Aided Design, 2002, pp. 583--586.

Digital Library

Cited By

Dinh QChen DWong MLin Y(2010)Dynamic power estimation for deep submicron circuits with process variationProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899860(587-592)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899860
Khalil DSinha DZhou HIsmail Y(2009)A timing-dependent power estimation framework considering couplingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200873917:6(843-847)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2008739
Sathanur APullini ABenini LMacii AMacii EPoncino MMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Timing-driven row-based power gatingProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283803(104-109)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283803
Show More Cited By

Index Terms

A timing dependent power estimation framework considering coupling
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Digital switches
      1. Logic families

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cover image ACM Conferences

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 05 November 2006

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ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Dinh QChen DWong MLin Y(2010)Dynamic power estimation for deep submicron circuits with process variationProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899860(587-592)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899860
Khalil DSinha DZhou HIsmail Y(2009)A timing-dependent power estimation framework considering couplingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200873917:6(843-847)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2008739
Sathanur APullini ABenini LMacii AMacii EPoncino MMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Timing-driven row-based power gatingProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283803(104-109)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283803
Fatemi HAmelifar BPedram MMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Power optimal MTCMOS repeater insertion for global busesProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283802(98-103)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283802

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