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A unified non-rectangular device and circuit simulation model for timing and power

Published: 05 November 2006 Publication History

Abstract

For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit characterizations for the post-OPC non-ideal-shape wafer images, with significant impacts on timing and power. Most of them, however, are based on the equivalent gate length models, which are different for timing and leakage, and thus hard to use for coherent circuit simulations. In this paper, we propose a unified post-litho device characterization model and circuit simulation for timing and power. To our best knowledge, this is the most accurate methodology for post-litho analysis, including timing, leakage and transient simulation. Based on this method, the parameter extraction is also included in the model which was omitted by previous works. A post-litho model card is proposed for circuit simulation to combine these two techniques. Our experimental results validate the new model.

References

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Cited By

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  • (2013)Design for Manufacturing With Emerging NanolithographyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.227675132:10(1453-1472)Online publication date: 1-Oct-2013
  • (2013)Improving the Quality of Delay-Based PUFs via Optical Proximity CorrectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.227494032:12(1879-1891)Online publication date: 1-Dec-2013
  • (2012)On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correctionProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228379(96-105)Online publication date: 3-Jun-2012
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  1. A unified non-rectangular device and circuit simulation model for timing and power

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    cover image ACM Conferences
    ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
    November 2006
    147 pages
    ISBN:1595933891
    DOI:10.1145/1233501
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 05 November 2006

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    Author Tags

    1. VLSI CAD
    2. device modeling
    3. physical design

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    View all
    • (2013)Design for Manufacturing With Emerging NanolithographyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.227675132:10(1453-1472)Online publication date: 1-Oct-2013
    • (2013)Improving the Quality of Delay-Based PUFs via Optical Proximity CorrectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.227494032:12(1879-1891)Online publication date: 1-Dec-2013
    • (2012)On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correctionProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228379(96-105)Online publication date: 3-Jun-2012
    • (2012)A Physical Model for Grain-Boundary-Induced Threshold Voltage Variation in Polysilicon Thin-Film TransistorsIEEE Transactions on Electron Devices10.1109/TED.2012.220538759:9(2396-2402)Online publication date: Sep-2012
    • (2012)DREIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.219247731:9(1379-1392)Online publication date: 1-Sep-2012
    • (2011)Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge RoughnessIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.204369419:6(987-996)Online publication date: 1-Jun-2011
    • (2011)Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage MinimizationIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2011.21592861:2(150-159)Online publication date: Jun-2011
    • (2010)A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effectsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899874(651-656)Online publication date: 18-Jan-2010
    • (2010)Modeling and analysis of the nonrectangular gate effect for postlithography circuit simulationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201363018:4(666-670)Online publication date: 1-Apr-2010
    • (2010)Performance-based optical proximity correction methodologyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203236029:1(51-64)Online publication date: 1-Jan-2010
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