Article

System-level process-driven variability analysis for single and multiple voltage-frequency island systems

Authors:

Diana Marculescu,

Siddharth GargAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 541 - 546

https://doi.org/10.1145/1233501.1233611

Published: 05 November 2006 Publication History

Abstract

The problem of determining bounds for application completion times running on generic systems comprised of single or multiple voltage-frequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-driven variability. The approach provides an exact solution for the system-level timing yield in single clock, single voltage (SSV) and VFI systems with an underlying tree-based topology, and a tight upper bound for generic, non-tree based topologies. The results show that: (a) timing yield for overall source-to- sink completion time for generic systems can be modeled in an exact manner for both SSV and VFI systems; and (b) multiple VFI, latency-constrained systems can achieve 11--90% higher timing yield than their SSV counterparts. The results are proven formally and supported by experimental results on two embedded applications, namely software defined radio and MPEG2 encoder.

References

[1]

X. Li, J. Le, P. Gopalakrishnan, L. T. Pileggi, "Asymptotic Probability Extraction for Non-Normal Distributions of Circuit Performance," in Proc. IEEE/ACM Intl. Conference on Computer Aided Design (ICCAD), San Jose, CA, Nov. 2004.

Digital Library

[2]

M. Orshansky and A. Bandyopadhyay, "Fast Statistical Timing Analysis Handling Arbitrary Delay Correlations," in Proc. ACM/IEEE Design Automation Conference (DAC), San Diego, CA, June 2004.

Digital Library

[3]

H. Chang, S. S. Sapatnekar, "Statistical Timing Analysis Considering Spatial Correlations Using A Single PERT-like Traversal," in Proc. IEEE/ACM Intl. Conference on Computer Aided Design (ICCAD), San Jose, CA, Nov. 2003.

Digital Library

[4]

I. A. Ferzli, F. N. Najm, "Statistical Estimation of Leakage-Induced Power Grid Voltage Drop Considering Within-Die Process Variations," in Proc. ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, June 2003.

Digital Library

[5]

K. Niyogi, D. Marculescu, "Speed and Voltage Selection for GALS Systems Based on Voltage/Frequency Islands," in Proc. ACM/IEEE Asian-South Pacific Design Automation Conference (ASPDAC), Shanghai, China, Jan.2005.

Digital Library

[6]

H. Wu, I.-M. Liu, M. D. F. Wong, Y. Wang, "Post-Placement Voltage Island Generation Under Performance Requirement," Proc. IEEE/ACM Intl. Conference on Computer Aided Design (ICCAD), San Jose, CA, Nov. 2005.

Digital Library

[7]

J. Hu, Y. Shin, N. Dhanwada, and R. Marculescu, "Architecting Voltage Islands in Core-based System-on-a-Chip Designs," in ACM/IEEE Intl. Symposium on Low Power Electronics and Design (ISLPED), Newport Beach, CA, Aug. 2004.

Digital Library

[8]

A. W. Shogan, "Bounding distributions for a stochastic PERT network," Networks 7 (1977) 359--381.

[9]

B. Dodin, "Bounding the project completion time distribution in PERT networks," Oper. Res. 33 (4) (1985) 862--881.

Digital Library

[10]

W. Kleinöder, "Stochastic analysis of parallel programs for hierarchical multiprocessor systems," Ph.D. Thesis, University of Erlangen, Nürnberg, 1982.

[11]

M. Colajanni, F. Lo Presti, S. Tucci, "A hierarchical approach for bounding the completion time distribution of stochastic task graphs," Performance Evaluation 41 (2000) 1--22.

Digital Library

[12]

J. Y. Brunel, W. M. Kruijtzer, P. Lieverse, K. A. Vissers, "YAPI: Application modeling for signal processing systems," in Proc. ACM/IEEE Design Automation Conference (DAC), Los Angeles, CA, June 2000.

Digital Library

[13]

"IBM Blue Logic Cu-08 voltage islands" http://www.ibm.com/chips/products/asics/products/visland.html.

[14]

L. S. Nielson, C. Niessen, J. Sparso, and K. Van Berkel, "Low-power operation using self timed circuits and adaptive scaling of the supply voltage," in IEEE Transactions on Very large Scale Integration (VLSI) Systems, 2 (4):391--397, December 1994.

Digital Library

[15]

J. Muttersbach, T. Villiger, and W. Fichtner, "Practical design of globally asynchronous locally synchronous systems," in Proc. Intl Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), April 2000.

Digital Library

[16]

T. Chelcea and S. M. Nowick, "A low latency fifo for mixed-clock systems," In Proc. of IEEE Computer Society Workshop on VLSI (WVLSI), April 2000.

Digital Library

[17]

A. Dasdan, "Rate Analysis of Embedded Systems," Ph.D. thesis, University of Illinois at Urbana Champagne, 1998.

[18]

K. A. Bowman, S. G. Duvall, J. D. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," in IEEE Journal of Solid State Circuits (JSSC), 37 (2):183--190, Feb. 2002.

[19]

D. Stoyan, "Comparison Methods for Queues and Other Stochastic Models," John Wiley, New York, 1983.

[20]

R. E. Barlow, F. Proshan, "Statistical Theory of Reliability and Life Testing," Hold, New York, 1975.

[21]

F. Lo Presti, M. Colajanni, S. Tucci, "Stochastic bounds on execution times of parallel computations," in Proc. of the IEEE Second International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, Durham, NC, February 1994.

Digital Library

[22]

D. Marculescu, S. Garg, "Variability Analysis for Single and Multiple Voltage-Frequency Island Systems," Technical Report CMU CSSI-06-09, April 2006.

[23]

S. Nassif, "Design for variability in DSM technologies," in Proc. IEEE International Symposium on Quality Electronic Design (ISQED), March 2000.

Digital Library

Cited By

Meyer BHartman AThomas D(2014)Cost-effective lifetime and yield optimization for NoC-based MPSoCsACM Transactions on Design Automation of Electronic Systems10.1145/253557519:2(1-33)Online publication date: 28-Mar-2014
https://dl.acm.org/doi/10.1145/2535575
Garg SMarculescu DMarculescu R(2012)Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chipACM Journal on Emerging Technologies in Computing Systems10.1145/2367736.23677398:4(1-17)Online publication date: 30-Nov-2012
https://dl.acm.org/doi/10.1145/2367736.2367739
Wang FChen YNicopoulos CWu XXie YVijaykrishnan N(2011)Variation-Aware Task and Communication Mapping for MPSoC ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.207783030:2(295-307)Online publication date: 1-Feb-2011
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Index Terms

System-level process-driven variability analysis for single and multiple voltage-frequency island systems
1. Computing methodologies
  1. Modeling and simulation
2. Hardware
  1. Hardware validation

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cover image ACM Conferences

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2006

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ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Meyer BHartman AThomas D(2014)Cost-effective lifetime and yield optimization for NoC-based MPSoCsACM Transactions on Design Automation of Electronic Systems10.1145/253557519:2(1-33)Online publication date: 28-Mar-2014
https://dl.acm.org/doi/10.1145/2535575
Garg SMarculescu DMarculescu R(2012)Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chipACM Journal on Emerging Technologies in Computing Systems10.1145/2367736.23677398:4(1-17)Online publication date: 30-Nov-2012
https://dl.acm.org/doi/10.1145/2367736.2367739
Wang FChen YNicopoulos CWu XXie YVijaykrishnan N(2011)Variation-Aware Task and Communication Mapping for MPSoC ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.207783030:2(295-307)Online publication date: 1-Feb-2011
https://dl.acm.org/doi/10.1109/TCAD.2010.2077830
Meyer BHartman AThomas D(2010)Slack allocation for yield improvement in NoC-based MPSoCs2010 11th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2010.5450496(738-746)Online publication date: Mar-2010
https://doi.org/10.1109/ISQED.2010.5450496
Garg SMarculescu DBenini LDe Micheli GAl-Hashimi BMueller W(2009)System-level process variability analysis and mitigation for 3D MPSoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874772(604-609)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874772
Chandra SLahiri KRaghunathan ADey S(2009)Variation-tolerant dynamic power management at the system-levelIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201980317:9(1220-1232)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1109/TVLSI.2009.2019803
Garg SMarculescu D(2009)System-level process variability analysis and mitigation for 3D MPSoCs2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090739(604-609)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090739
Singhal LBozorgzadeh ENassif SRoychowdhury J(2008)Process variation aware system-level task allocation using stochastic ordering of delay distributionsProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509583(570-574)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509583
Wang FWu XXie YKyung CChoi KHa S(2008)Variability-driven module selection with joint design time optimization and post-silicon tuningProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356806(2-9)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356806
Wang FSun GXie YSciuto D(2008)A variation aware high level synthesis frameworkProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403630(1063-1068)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403630
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