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An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management

Published: 05 November 2006 Publication History

Abstract

As CMOS technology scales into the nanometer regime, power dissipation and associated thermal concerns in high-performance ICs due to on-chip hot-spots and thermal gradients are beginning to impact VLSI design. Moreover, elevated substrate (junction or die) temperature strongly influences IC performance, reliability, and packaging/cooling cost. Hence, accurate estimation of substrate thermal profiles is critical. This paper presents an accurate chip-level electrothermally-aware methodology for spatial silicon substrate temperature estimation. The methodology self-consistently incorporates various electrothermal couplings arising mainly due to the strong dependence of subthreshold leakage on temperature and also employs an accurate package thermal model, to account for inhomogeneous layers and non-cubic structure, which are not considered in traditional methods. The proposed methodology becomes increasingly effective as technology scales due to increasing leakage. Furthermore, it is shown that considering realistic package thermal models not only improves the accuracy of estimating temperature distribution but also has significant implications for power estimation and hot-spot management.

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Cited By

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  • (2017)Power pre-characterized meshing algorithm for finite element thermal analysis of integrated circuitsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130684(1293-1296)Online publication date: 27-Mar-2017
  • (2010)Temperature-Aware Leakage Estimation Using Piecewise Linear Power ModelsIEICE Transactions on Electronics10.1587/transele.E93.C.1679E93-C:12(1679-1691)Online publication date: 2010
  • (2010)Power DissipationLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_2(41-80)Online publication date: 25-Oct-2010
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  1. An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management

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          cover image ACM Conferences
          ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
          November 2006
          147 pages
          ISBN:1595933891
          DOI:10.1145/1233501
          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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          Published: 05 November 2006

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          View all
          • (2017)Power pre-characterized meshing algorithm for finite element thermal analysis of integrated circuitsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130684(1293-1296)Online publication date: 27-Mar-2017
          • (2010)Temperature-Aware Leakage Estimation Using Piecewise Linear Power ModelsIEICE Transactions on Electronics10.1587/transele.E93.C.1679E93-C:12(1679-1691)Online publication date: 2010
          • (2010)Power DissipationLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_2(41-80)Online publication date: 25-Oct-2010
          • (2008)Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal powerIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200129716:12(1609-1619)Online publication date: 1-Dec-2008

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