Article

Design and integration methods for a multi-threaded dual core 65nm Xeon® processor

Authors:

Raj Varada,

Mysore Sriram,

Kris Chou,

James GuzzoAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 607 - 610

https://doi.org/10.1145/1233501.1233626

Published: 05 November 2006 Publication History

Get Access

Abstract

The success of building a complex multi-billion transistor processor is very dependent on robust and silicon proven design and integration methods. The complexity of 65nm process and striving for best in class performance with aggressive time to market schedule put a heavy emphasis on innovative design and integration methods to enable working silicon. In this paper, we describe the design and integration methods successfully used in a multi-threaded dual core 65nm Xeon® Processor.

Index Terms---Design Methods; Integration; processor; Xeon®.

References

[1]

Hyper-Threading Technology, Intel Technology Journal, Vol. 6 Issue 1, Feb 2002

Google Scholar

[2]

S. Rusu, S. Tam, H. Muljono, D. Ayers, J. Chang, "A Dual-Core Multi-Threaded Xeon® Processor with 16MB L3 Cache", International Solid State Circuits Conference, pp 102--104, January 2006.

Google Scholar

[3]

J. Chang, J. Shoemaker, M. Haque, M. Huang, K. Truong, M. Karim, S. Chiu, G. Leong, K. Desai, R. Goe, S. Kulkarni, A. Rao, D. Hannoun, S. Rusu, "A 0.13/spl mu/m triple-Vt 9MB third level on-die cache for the Itanium/spl reg/2 processor", International Solid State Circuits Conference, January 2004.

Google Scholar

Cited By

View all

Muhammad HSagahyroon A(2009)Virtual prototyping and performance analysis of two memory architecturesEURASIP Journal on Embedded Systems10.1155/2009/9848912009(1-1)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1155/2009/984891
Thoziyoor SAhn JMonchiero MBrockman JJouppi N(2008)A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory HierarchiesACM SIGARCH Computer Architecture News10.1145/1394608.138212736:3(51-62)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1145/1394608.1382127
Thoziyoor SAhn JMonchiero MBrockman JJouppi N(2008)A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory HierarchiesProceedings of the 35th Annual International Symposium on Computer Architecture10.1109/ISCA.2008.16(51-62)Online publication date: 21-Jun-2008
https://dl.acm.org/doi/10.1109/ISCA.2008.16

Index Terms

Design and integration methods for a multi-threaded dual core 65nm Xeon® processor
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware
  1. Emerging technologies
  2. Very large scale integration design

Recommendations

Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition 2nd Edition
Performance analysis of multi-threaded multi-core CPUs
MES '13: Proceedings of the First International Workshop on Many-core Embedded Systems

Processors are constantly changing and becoming more advanced. They incorporate new concepts and ideas into the architecture with each evolution. One such concept is multi-threading. It aims at increasing the processors performance by reducing its idle ...
Hybrid multi-core architecture for boosting single-threaded performance

The scaling of technology and the diminishing return of complicated uniprocessors have driven the industry towards multicore processors. While multithreaded applications can naturally leverage the enhanced throughput of multi-core processors, a large ...

Comments

Information & Contributors

Information

Published In

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2006

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ICCAD06

Sponsor:

SIGDA
IEEE-CAS
IEEE-CS

ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
310
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 07 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Muhammad HSagahyroon A(2009)Virtual prototyping and performance analysis of two memory architecturesEURASIP Journal on Embedded Systems10.1155/2009/9848912009(1-1)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1155/2009/984891
Thoziyoor SAhn JMonchiero MBrockman JJouppi N(2008)A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory HierarchiesACM SIGARCH Computer Architecture News10.1145/1394608.138212736:3(51-62)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1145/1394608.1382127
Thoziyoor SAhn JMonchiero MBrockman JJouppi N(2008)A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory HierarchiesProceedings of the 35th Annual International Symposium on Computer Architecture10.1109/ISCA.2008.16(51-62)Online publication date: 21-Jun-2008
https://dl.acm.org/doi/10.1109/ISCA.2008.16

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition 2nd Edition

Performance analysis of multi-threaded multi-core CPUs

Hybrid multi-core architecture for boosting single-threaded performance

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations