Studying a GALS FPGA architecture using a parameterized automatic design flow
Authors: 
Xin Jia, Ranga VemuriAuthors Info & Claims
Xin Jia, Ranga VemuriAuthors Info & ClaimsPages 688 - 693
Abstract
Routing delays dominate other delays in current FPGA designs. We have proposed a novel Globally Asynchronous Locally Synchronous (GALS) FPGA architecture called the GAPLA to deal with this problem. In the GAPLA architecture, The FPGA area is divided into locally synchronous blocks and the communications between them are through asynchronous I/O interfaces. An automatic design flow is developed for the GAPLA architecture. Starting from behavioral description, a design is partitioned into smaller modules and fit to GAPLA synchronous blocks. The asynchronous communications between modules are then sytthesized. The CAD flow is parameterized in modeling the GAPLA architecture. By manipulating the parameters, we could study different factors of the designed GAPLA arcitecturc. Our experimental results show an average of 20% performance improvement could be achieved by the GAPLA architecture.
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Index Terms
- Studying a GALS FPGA architecture using a parameterized automatic design flow
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Published: 05 November 2006
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ICCAD06: The International Conference on Computer-Aided Design 2006
November 5 - 9, 2006
California, San Jose
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