Article

High-level synthesis challenges and solutions for a dynamically reconfigurable processor

Authors:

Noritsugu Nakamura,

Yoshinosuke Kato,

Kazutoshi Wakabayashi,

Li JingAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 702 - 708

https://doi.org/10.1145/1233501.1233647

Published: 05 November 2006 Publication History

Abstract

A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone finite state machine and that switches "contexts" consisting of many operational and storage units in processing elements (PEs) and wires between them. Utilizing the resources not only in two spatial dimensions but also vertically (time-multiplexed) under accurate timing and area constraints imposes challenges for a high-level synthesizer for the DRP. We describe a C-based behavioral synthesis method which features data path generation with clock speed optimization. This is achieved by including the overhead of selectors in the scheduling algorithm, and considering a wire delay at each PE level. A new technique is introduced to achieve high area efficiency. It works by effectively allocating multiple steps into the context. From the original highlevel synthesizer for application-specific integrated circuits, some of the basic rules such as operator and register sharing were completely changed due to the coarse grained and multi-context architecture. Experimental results show that the generated data paths are highly parallelized and well balanced between contexts. The delay controllability enables the highest throughput point to be found more easily.

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Cited By

Kim CJeong SCho SLee YSong WKim YKim HLee J(2021)Thread-aware area-efficient high-level synthesis compiler for embedded devicesProceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO51591.2021.9370341(327-339)Online publication date: 27-Feb-2021
https://dl.acm.org/doi/10.1109/CGO51591.2021.9370341
Ishii YYabuuchi MSawada YMorimoto MTsukamoto YYoshida YShibata KSano TTanaka SNii K(2016) A 5.92-Mb/mm 2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)10.1109/ASSCC.2016.7844124(17-20)Online publication date: Nov-2016
https://doi.org/10.1109/ASSCC.2016.7844124
Ren H(2014)A brief introduction on contemporary High-Level Synthesis2014 IEEE International Conference on IC Design & Technology10.1109/ICICDT.2014.6838614(1-4)Online publication date: May-2014
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Index Terms

High-level synthesis challenges and solutions for a dynamically reconfigurable processor
1. Hardware

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cover image ACM Conferences

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 November 2006

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ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

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Cited By

Kim CJeong SCho SLee YSong WKim YKim HLee J(2021)Thread-aware area-efficient high-level synthesis compiler for embedded devicesProceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO51591.2021.9370341(327-339)Online publication date: 27-Feb-2021
https://dl.acm.org/doi/10.1109/CGO51591.2021.9370341
Ishii YYabuuchi MSawada YMorimoto MTsukamoto YYoshida YShibata KSano TTanaka SNii K(2016) A 5.92-Mb/mm 2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)10.1109/ASSCC.2016.7844124(17-20)Online publication date: Nov-2016
https://doi.org/10.1109/ASSCC.2016.7844124
Ren H(2014)A brief introduction on contemporary High-Level Synthesis2014 IEEE International Conference on IC Design & Technology10.1109/ICICDT.2014.6838614(1-4)Online publication date: May-2014
https://doi.org/10.1109/ICICDT.2014.6838614
Mitsuyama YOnodera H(2014)Variability and Soft-Error Resilience in Dependable VLSI PlatformProceedings of the 2014 IEEE 23rd Asian Test Symposium10.1109/ATS.2014.20(45-50)Online publication date: 16-Nov-2014
https://dl.acm.org/doi/10.1109/ATS.2014.20
Wakabayashi KTakenaka TInoue H(2014)Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPU2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2014.6742903(282-284)Online publication date: Jan-2014
https://doi.org/10.1109/ASPDAC.2014.6742903
Han KChoi KLee JMacii E(2013)Compiling control-intensive loops for CGRAs with state-based full predicationProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485663(1579-1582)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485663
Kondratyev ALavagno LMeyer MWatanabe YMacii E(2013)Share with careProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485657(1547-1552)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485657
Bergmann NShukla SBecker J(2013)QUKUACM Transactions on Embedded Computing Systems10.1145/2435227.243525912:1s(1-26)Online publication date: 29-Mar-2013
https://dl.acm.org/doi/10.1145/2435227.2435259
Konoura HAlnajjar DMitsuyama YOchi HImagawa TNoda SWakabayashi KHashimoto MOnoye T(2013)Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2013.6732309(1-6)Online publication date: Dec-2013
https://doi.org/10.1109/ReConFig.2013.6732309
Toi TNakamura NFujii TKitaoka TTogawa KFuruta KAwashima T(2013)Optimizing time and space multiplexed computation in a dynamically reconfigurable processor2013 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2013.6718338(106-111)Online publication date: Dec-2013
https://doi.org/10.1109/FPT.2013.6718338
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