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A code refinement methodology for performance-improved synthesis from C

Published: 05 November 2006 Publication History

Abstract

Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffers due to the use of C constructs and coding practices that are not appropriate for hardware. Most previous approaches to addressing this problem require drastic changes to coding practice. We present an approach that instead requires only minimal changes but yields significant speedups. In this approach, a software developer initially writes C code as they normally would, and then applies simple refinement guidelines to only the performance-critical code regions, which are the regions most likely to be synthesized to hardware. Alternatively, if a designer is aware of performance-critical parts of the application, the guidelines could be followed during development. In this study, we analyze dozens of embedded benchmarks to determine the most common C coding practices that limit hardware performance, and introduce coding guidelines to make the code more amenable to synthesis. Those guidelines typically require minimal coding effort, generally consisting of less than ten lines of code for each guideline. The guidelines typically represent modifications that require designer knowledge, making the guidelines difficult or impossible for synthesis tools to automate. We apply these guidelines to six benchmarks, resulting in average speedups of 3.5x compared to synthesis from the original code with a negligible software size and performance overhead.

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    cover image ACM Conferences
    ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
    November 2006
    147 pages
    ISBN:1595933891
    DOI:10.1145/1233501
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 05 November 2006

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    Author Tags

    1. FPGA
    2. code refinement
    3. coding guidelines
    4. compilation
    5. embedded systems
    6. hardware/software partitioning
    7. synthesis

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    • (2016)High Level Synthesis of Complex ApplicationsProceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2847263.2847274(224-233)Online publication date: 21-Feb-2016
    • (2014)A framework for dynamic parallelization of FPGA-accelerated applicationsProceedings of the 17th International Workshop on Software and Compilers for Embedded Systems10.1145/2609248.2609256(1-10)Online publication date: 10-Jun-2014
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