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Leveraging protocol knowledge in slack matching

Published: 05 November 2006 Publication History

Abstract

Stalls, due to mis-matches in communication rates, are a major performance obstacle in pipelined circuits. If the rate of data production is faster than the rate of consumption, the resulting design performs slower than when the communication rate is matched. This can be remedied by inserting pipeline buffers (to temporarily hold data), allowing the producer to proceed if the consumer is not ready to accept data. The problem of deciding which channels need these buffers (and how many) for an arbitrary communication profile is called the slack matching problem; the optimal solution to this problem has been shown to be NP-complete.
In this paper, we present a heuristic that uses knowledge of the communication protocol to explicitly model these bottlenecks, and an iterative algorithm to progressively remove these bottlenecks by inserting buffers. We apply this algorithm to asynchronous circuits, and show that it naturally handles large designs with arbitrarily cyclic and acyclic topologies, which exhibit various types of control choice. The heuristic is efficient, achieving linear time complexity in practice, and produces solutions that (a) achieve up to 60% performance speedup on large media processing kernels, and (b) can either be verified to be optimal, or the approximation margin can be bounded.

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Cited By

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  • (2021)Buffer Placement and Sizing for High-Performance Dataflow CircuitsACM Transactions on Reconfigurable Technology and Systems10.1145/347705315:1(1-32)Online publication date: 9-Nov-2021
  • (2016)Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuitsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972051(1042-1047)Online publication date: 14-Mar-2016
  • (2015)De-elastisationProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755813(273-276)Online publication date: 9-Mar-2015
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cover image ACM Conferences
ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
November 2006
147 pages
ISBN:1595933891
DOI:10.1145/1233501
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 November 2006

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Cited By

View all
  • (2021)Buffer Placement and Sizing for High-Performance Dataflow CircuitsACM Transactions on Reconfigurable Technology and Systems10.1145/347705315:1(1-32)Online publication date: 9-Nov-2021
  • (2016)Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuitsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972051(1042-1047)Online publication date: 14-Mar-2016
  • (2015)De-elastisationProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755813(273-276)Online publication date: 9-Mar-2015
  • (2013)Slack matching mode-based asynchronous circuits for average-case performanceProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561873(219-225)Online publication date: 18-Nov-2013
  • (2009)Elastic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203043628:10(1437-1455)Online publication date: 1-Oct-2009
  • (2009)Synthesis and optimization of pipelined packet processorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200916828:2(231-244)Online publication date: 1-Feb-2009
  • (2009)High performance asynchronous design flow using a novel static performance analysis methodComputers and Electrical Engineering10.1016/j.compeleceng.2008.11.02535:6(920-941)Online publication date: 1-Nov-2009
  • (2008)Performance estimation and slack matching for pipelined asynchronous architectures with choiceProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509560(449-456)Online publication date: 10-Nov-2008
  • (2008)Slack analysis in the system design loopProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450189(231-236)Online publication date: 19-Oct-2008
  • (2007)Operation chaining asynchronous pipelined circuitsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326165(442-449)Online publication date: 5-Nov-2007
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