Strategies for branch target buffers

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Strategies for branch target buffers

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International Symposium on Microarchitecture archive
Proceedings of the 24th annual international symposium on Microarchitecture table of contents

Albuquerque, New Mexico, Puerto Rico

Pages: 42 - 50

Year of Publication: 1991

ISBN:0-89791-460-0

Authors

Brian K. Bray	Computer Systems Laboratory, Stanford University, CA
M. J. Flynn	Computer Systems Laboratory, Stanford University, CA

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 16, Citation Count: 7

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Fis81	J. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions Computer, C-30(7):478-490, July 1981.
	HC89	W. W. Hwu , P. P. Chang, Achieving high instruction cache performance with an optimizing compiler, Proceedings of the 16th annual international symposium on Computer architecture, p.242-251, April 1989, Jerusalem, Israel
	Hil88	Mark D. Hill, A Case for Direct-Mapped Caches, Computer, v.21 n.12, p.25-40, December 1988 [doi>10.1109/2.16187 ]
	Joh89	William M. Johnson, Super-Scalar Processor Design, Stanford University, Stanford, CA, 1989
	LS84	J. ~ and A. J. Smith. Branch Prediction Strategies and Branch Target Buffer Design. IEEE Computer, 17(1):6-22, January 1984.
	Smi81	James E. Smith, A study of branch prediction strategies, Proceedings of the 8th annual symposium on Computer Architecture, p.135-148, May 12-14, 1981, Minneapolis, Minnesota, United States

CITED BY 7

	Dennis Lee , Jean-Loup Baer , Brad Calder , Dirk Grunwald, Instruction cache fetch policies for speculative execution, ACM SIGARCH Computer Architecture News, v.23 n.2, p.357-367, May 1995
	Brad Calder , Dirk Grunwald, Next cache line and set prediction, ACM SIGARCH Computer Architecture News, v.23 n.2, p.287-296, May 1995
	B. Calder , D. Grunwald, Fast and accurate instruction fetch and branch prediction, ACM SIGARCH Computer Architecture News, v.22 n.2, p.2-11, April 1994
	Tse-Yu Yeh , Yale N. Patt, Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors, Proceedings of the 26th annual international symposium on Microarchitecture, p.164-175, December 01-03, 1993, Austin, Texas, United States
	Amit Mital , Barry Fagin, The Performance of Counter- and Correlation-Based Schemes for Branch Target Buffers, IEEE Transactions on Computers, v.44 n.12, p.1383-1393, December 1995
	Sang-hyuk Lee , Il-kwan Kim , Lynn Choi, Branch predictor design and performance estimation for a high performance embedded microprocessor, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Brad Calder , Dirk Grunwald, Reducing branch costs via branch alignment, ACM SIGPLAN Notices, v.29 n.11, p.242-251, Nov. 1994

INDEX TERMS

Primary Classification:
D. Software
D.3 PROGRAMMING LANGUAGES
D.3.4 Processors
Subjects: Optimization

Additional Classification:
C. Computer Systems Organization
C.4 PERFORMANCE OF SYSTEMS
Subjects: Performance attributes

General Terms:
Measurement, Performance, Theory

Collaborative Colleagues:

Brian K. Bray: colleagues

M. J. Flynn: colleagues

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