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Nonblocking transactions without indirection using alert-on-update

Published: 09 June 2007 Publication History

Abstract

Nonblocking implementations of software transactional memory (STM) typically impose an extra level of indirection when accessing an object; some researchers have claimed that the cost of this indirection outweighs the semantic advantages of nonblocking progress guarantees. We consider this claim in the context of a simple hardware assist, alert-on-update (AOU), which allows a thread to request immediate notification if specified line(s) are replaced or invalidated in its cache. We show that even a single AOU line allows us to construct a simple, nonblocking STM system without extra indirection. At the same time, we observe that per-load validation operations, required for intra-object consistency in both the new system and in lock-based (blocking) STM, at least partially negate the resulting performance gain. Moreover, inter-object consistency checks, also required in both kinds of systems, remain the dominant cost for transactions that access many objects. We therefore present a second nonblocking STM system that uses multiple AOU lines (one per accessed object) to eliminate validation overhead entirely, resulting in a nonblocking, zero-indirection STM system that outperforms competing systems by as much as a factor of 2.

References

[1]
A.-R. Adl-Tabatabai, B. T. Lewis, V. Menon, B. R. Murphy, B. Saha, and T. Shpeisman. Compiler and Runtime Support for Efficient Software Transactional Memory. In Proc. of the SIGPLAN 2006 Conf. on Programming Language Design and Implementation, Ottawa, ON, Canada, June 2006.
[2]
D. Dice, O. Shalev, and N. Shavit. Transactional Locking II. In Proc. of the 20th Intl. Symp. on Distributed Computing, Stockholm, Sweden, Sept. 2006.
[3]
D. Dice and N. Shavit. What Really Makes Transactions Fast? In ACM SIGPLAN Workshop on Transactional Computing, Ottawa, ON, Canada, June 2006.
[4]
R. Ennals. Software Transactional Memory Should Not Be Lock Free. Technical Report IRC-TR-06-052, Intel Research Cambridge, 2006.
[5]
K. Fraser and T. Harris. Concurrent Programming Without Locks. Submitted for publication, 2004. Available as research.microsoft.com/¿tharris/drafts/cpwl-submission.pdf.
[6]
R. Guerraoui, M. Herlihy, and B. Pochon. Polymorphic Contention Management in SXM. In Proc. of the 19th Intl. Symp. on Distributed Computing, Cracow, Poland, Sept. 2005.
[7]
T. Harris and K. Fraser. Language Support for Lightweight Transactions. In OOPSLA 2003 Conf. Proc., Anaheim, CA, Oct. 2003.
[8]
T. Harris and K. Fraser. Revocable Locks for Non-Blocking Programming. In Proc. of the 10th ACM Symp. on Principles and Practice of Parallel Programming, Chicago, IL, June 2005.
[9]
T. Harris, M. Plesko, A. Shinnar, and D. Tarditi. Optimizing Memory Transactions. In Proc. of the SIGPLAN 2006 Conf. on Programming Language Design and Implementation, Ottawa, ON, Canada, June 2006.
[10]
M. Herlihy, V. Luchangco, and M. Moir. Obstruction-Free Synchronization: Double-Ended Queues as an Example. In Proc. of the 23rd Intl. Conf. on Distributed Computing Systems, Providence, RI, May, 2003.
[11]
M. Herlihy, V. Luchangco, M. Moir, and W. N. Scherer III. Software Transactional Memory for Dynamic-sized Data Structures. In Proc. of the 22nd ACM Symp. on Principles of Distributed Computing, Boston, MA, July 2003.
[12]
V. J. Marathe, W. N. Scherer III, and M. L. Scott. Adaptive Software Transactional Memory. In Proc. of the 19th Intl. Symp. on Distributed Computing, Cracow, Poland, Sept. 2005.
[13]
V. J. Marathe, M. F. Spear, C. Heriot, A. Acharya, D. Eisenstat, W. N. Scherer III, and M. L. Scott. Lowering the Overhead of Software Transactional Memory. In ACM SIGPLAN Workshop on Transactional Computing, Ottawa, ON, Canada, June 2006. Expanded version available as TR 893, Dept. of Computer Science, Univ. of Rochester, Mar. 2006.
[14]
V. Marathe and M. Moir. An Efficient Nonblocking Copyback Mechanism in Hybrid Transactional Memory (poster paper). In Proc. of the 12th ACM Symp. on Principles and Practice of Parallel Programming, San Jose, CA, Mar. 2007.
[15]
M. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood. Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset. In ACM SIGARCH Computer Architecture News, Sept. 2005.
[16]
K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. LogTM: Log-based Transactional Memory. In Proc. of the 12th Intl. Symp. on High Performance Computer Architecture, Austin, TX, Feb. 2006.
[17]
B. Saha, A.-R. Adl-Tabatabai, and Q. Jacobson. Architectural Support for Software Transactional Memory. In Proc. of the 39th Intl. Symp. on Microarchitecture, Dec. 2006. Orlando, FL.
[18]
B. Saha, A.-R. Adl-Tabatabai, R. L. Hudson, C. C. Minh, and B. Hertzberg. McRT-STM: A High Performance Software Transactional Memory System for a Multi-Core Runtime. In Proc. of the 11th ACM Symp. on Principles and Practice of Parallel Programming, New York, NY, Mar. 2006.
[19]
W. N. Scherer III and M. L. Scott. Advanced Contention Management for Dynamic Software Transactional Memory. In Proc. of the 24th ACM Symp. on Principles of Distributed Computing, Las Vegas, NV, July 2005.
[20]
M. L. Scott. Sequential Specification of Transactional Memory Semantics. In ACM SIGPLAN Workshop on Transactional Computing, Ottawa, ON, Canada, June 2006.
[21]
A. Shriraman, V. J. Marathe, S. Dwarkadas, M. L. Scott, D. Eisenstat, C. Heriot, W. N. Scherer III, and M. F. Spear. Hardware Acceleration of Software Transactional Memory. In ACM SIGPLAN Workshop on Transactional Computing, Ottawa, ON, Canada, June 2006. Expanded version available as TR 887, Dept. of Computer Science, Univ. of Rochester, Dec. 2005, revised Mar. 2006.
[22]
M. F. Spear, V. J. Marathe, W. N. Scherer III, and M. L. Scott. Conflict Detection and Validation Strategies for Software Transactional Memory. In Proc. of the 20th Intl. Symp. on Distributed Computing, Stockholm, Sweden, Sept. 2006.
[23]
M. F. Spear, A. Shriraman, H. Hossain, S. Dwarkadas, and M. L. Scott. Alert-on-Update: A Communication Aid for Shared Memory Multiprocessors (poster paper). In Proc. of the 12th ACM Symp. on Principles and Practice of Parallel Programming, San Jose, CA, Mar. 2007.
[24]
C. Wang, W.-Y. Chen, Y. Wu, B. Saha, and A.-R. Adl-Tabatabai. Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language. In Proc. of the Intl. Symp. on Code Generation and Optimization, San Jose, CA, Mar. 2007.
[25]
The Rochester Software Transactional Memory Runtime. 2006. www.cs.rochester.edu/research/synchronization/rstm/.

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cover image ACM Conferences
SPAA '07: Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures
June 2007
376 pages
ISBN:9781595936677
DOI:10.1145/1248377
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 June 2007

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  1. event-based systems
  2. obstruction freedom
  3. software transactional memory

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Overall Acceptance Rate 447 of 1,461 submissions, 31%

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Cited By

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  • (2018)Transactional pre-abort handlers in hardware transactional memoryProceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques10.1145/3243176.3243186(1-11)Online publication date: 1-Nov-2018
  • (2018)Inherent limitations of hybrid transactional memoryDistributed Computing10.1007/s00446-017-0305-331:3(167-185)Online publication date: 1-Jun-2018
  • (2013)Shared-Memory SynchronizationSynthesis Lectures on Computer Architecture10.2200/S00499ED1V01Y201304CAC0238:2(1-221)Online publication date: 12-Jun-2013
  • (2013)Between all and nothing - versatile aborts in hardware transactional memoryProceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures10.1145/2486159.2486165(108-110)Online publication date: 23-Jul-2013
  • (2011)Optimizing hybrid transactional memoryProceedings of the twenty-third annual ACM symposium on Parallelism in algorithms and architectures10.1145/1989493.1989501(53-64)Online publication date: 4-Jun-2011
  • (2010)A scalable lock-free universal construction with best effort transactional hardwareProceedings of the 24th international conference on Distributed computing10.5555/1888781.1888790(50-63)Online publication date: 13-Sep-2010
  • (2010)Transactional Memory, 2nd editionSynthesis Lectures on Computer Architecture10.2200/S00272ED1V01Y201006CAC0115:1(1-263)Online publication date: 22-Dec-2010
  • (2010)A Scalable Lock-Free Universal Construction with Best Effort Transactional HardwareDistributed Computing10.1007/978-3-642-15763-9_6(50-63)Online publication date: 2010
  • (2009)Scalable nonblocking concurrent objects for mission critical codeProceedings of the 24th ACM SIGPLAN conference companion on Object oriented programming systems languages and applications10.1145/1639950.1639954(597-612)Online publication date: 25-Oct-2009
  • (2009)NZTMProceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures10.1145/1583991.1584048(204-213)Online publication date: 11-Aug-2009
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