Architectural implications of brick and mortar silicon manufacturing

ABSTRACT

We introduce a novel chip fabrication technique called "brick and mortar", in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified arrangement to an inter-brick communication backbone chip. The goal of brick and mortar assembly is to provide a low-overhead method to produce custom chips, yet with performance that tracks an ASIC more closely than an FPGA. This paper examines the architectural design choices in this chip-design system. These choices include the definition of reasonable bricks, both in functionality and size, as well as the communication interconnect that the I/O cap provides. To do this we synthesize candidate bricks, analyze their area and bandwidth demands, and present an architectural design for the inter-brick communication network. We discuss a sample chip design, a 16-way CMP, and analyze the costs and benefits of designing chips with brick and mortar. We find that this method of producing chips incurs only a small performance loss (8%) compared to a fully custom ASIC, which is significantly less than the degradation seen from other low-overhead chip options, such as FPGAs. Finally, we measure the effect that architectural design decisions have on the behavior of the proposed physical brick assembly technique, fluidic self-assembly.

REFERENCES

• 1: H. O. Alan Barber, Ken Lee. A bare-chip probe for high I/O, high speed testing. 1994.
• 2: Alien technology website. www.alientechnology.com.
• 3: Altera website. www.altera.com.
• 4: Ambric, Inc. website. www.ambric.com.
• 5: AMI semiconductor website. www.amis.com.
• 6: Amkor technology website. www.amkor.com.
• 7: Artisan website. www.artisan.org.
• 8: R. Ball. The promise of structured ASIC. Oct 2004. www.electronicsweekly.com.
• 9: K. Brown. Economic challenges on the path to 22 nm. June 2004. www.future-fab.com.
• 10: R. R. B.S. Landman. On a pin versus block relationship for partitions of logic graphs. Transactions on Computers, 1971.
• 11: D. Bursky. Arrays narrow platform ASIC, FPGA gap. July 2006. www.eetimes.com.
• 12: ChipX website. www.chipx.com.
• 13: T. Clark, R. Ferrigno, and et al. Template-directed self-assembly of 10-micron-sized hexagonal plates. 124, 2002.
• 14: Cradle technologies website. www.cradle.com.
• 15: Cswitch website. www.cswitch.com.
• 16: R. Drost, R. Hopkins, and I. Sutherland. Proximity communication. 2003.
• 17: eASIC website. www.easic.com.
• 18: Carl Ebeling , Darren C. Cronquist , Paul Franklin, RaPiD - Reconfigurable Pipelined Datapath, Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, p.126-135, September 23-25, 1996
• 19: J. U. Knickerbocker , P. S. Andry , L. P. Buchwalter , A. Deutsch , R. R. Horton , K. A. Jenkins , Y. H. Kwark , G. McVicker , C. S. Patel , R. J. Polastre , C. Schuster , A. Sharma , S. M. Sri-Jayantha , C. W. Surovic , C. K. Tsang , B. C. Webb , S. L. Wright , S. R. McKnight , E. J. Sprogis , B. Dang, Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection, IBM Journal of Research and Development, v.49 n.4/5, p.725-753, July 2005
• 20: K. K. et al. 1.27gb/s/pin 3mw/pin wireless superconnect (wsc) interface scheme. 2003.
• 21: R. F. Agahdel, C. Ho. Known good die: A practical solution. Apr 1993.
• 22: J. Fang and K. F. Böhringer. Wafer level packaging based on uniquely orienting self-assembly (the DUO-SPASS processes). 15, 2006.
• 23: Faraday electronics website. www.faradayelectronics.com.
• 24: Fujitsu website. www.fujitsu.com.
• 25: M. Heskins and J. Guillet. Solution properties of poly(N-isopropylacrylamide). A2:1441, 1968.
• 26: D. Huber, R. Manginell, M. Samara, B. Kim, and B. Bunker. Programmed adsorption and release of proteins in a microfluidic device. 301, 2003.
• 27: Ian Kuon , Jonathan Rose, Measuring the gap between FPGAs and ASICs, Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA [doi>10.1145/1117201.1117205]
• 28: Peter S. Magnusson , Magnus Christensson , Jesper Eskilson , Daniel Forsgren , Gustav Hållberg , Johan Högberg , Fredrik Larsson , Andreas Moestedt , Bengt Werner, Simics: A Full System Simulation Platform, Computer, v.35 n.2, p.50-58, February 2002 [doi>10.1109/2.982916 ]
• 29: Milo M. K. Martin , Daniel J. Sorin , Bradford M. Beckmann , Michael R. Marty , Min Xu , Alaa R. Alameldeen , Kevin E. Moore , Mark D. Hill , David A. Wood, Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset, ACM SIGARCH Computer Architecture News, v.33 n.4, November 2005 [doi>10.1145/1105734.1105747]
• 30: Mathstar, Inc. website. www.mathstar.com.
• 31: S. Mick, J. Wilson, and P. Franzon. 4Gbps high-density AC coupled interconnection. 2002.
• 32: Nec website. www.nec.com.
• 33: Takumi Okamoto , Tsutomu Kimoto , Naotaka Maeda, Design methodology and tools for NEC electronics' structured ASIC ISSP, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA [doi>10.1145/981066.981086]
• 34: Opencores.org website. www.opencores.org.
• 35: Y. Pan, R. Wesley, R. Luginbuhl, D. Denton, and B. Ratner. Plasma polymerized N-Isopropylacrylamide: Synthesis and characterization of a smart thermally responsive coating. 2, 2001.
• 36: J. M. Perkins. Magnetically assisted statistical assembly of III-V heterostructures on silicon: Initial process and technology development. 2002.
• 37: picochip website. www.picochip.com.
• 38: Quicksilver technology website. www.qstech.com.
• 39: J. T. R. Kalla, Sinharoy Balaram. IBM Power5 chip: a dual-core multithreaded processor. Micro, Mar-Apr 2004.
• 40: J. Rumpler. Optoelectronic integration using the magnetically assisted statistical assembly technique: Initial magnetic characterization and process development. 2002.
• 41: J. Rumpler, M. Perkins, and et al. Optoelectronic integration using statistical assembly and magnetic retention of heterostructure pills. 2, 2004.
• 42: D. Saltzman and J. Knight, T. Capacitive coupling solves the known good die problem. 1994.
• 43: E. Schuman. Rfid bellwether alien again postpones its ipo. July 2006. www.eweek.com.
• 44: Jaswinder Pal Singh , Wolf-Dietrich Weber , Anoop Gupta, SPLASH: Stanford parallel applications for shared-memory, ACM SIGARCH Computer Architecture News, v.20 n.1, p.5-44, March 1992 [doi>10.1145/130823.130824]
• 45: Software/hardware generation for dsp algorithms. ttp://www.spiral.net.
• 46: http://www-vlsi.stanford.edu/ee272/proj99/babyviterbi/verilogcode.html.
• 47: Sun ultrasparc-t1. http://www.sun.com/processors/UltraSPARC-T1/.
• 48: R. R. A. Syms, E. M. Yeatman, and et al. Surface tension-powered self-assembly of microstrutures: The state-of-the-art. 12, 2003.
• 49: Synopsys website. http://www.synopsys.com.
• 50: TSMC 90nm technology platform. http://www.tsmc.com/download/english/a05 literature/90nm Brochure.pdf.
• 51: N. Tuck, T. Sherwood, B. Calder, and G. Varghese. Deterministic memory-efficient string matching algorithms for intrusion detection. In Infocom Conference, 2004.
• 52: Kun-Cheng Wu , Yu-Wen Tsai, Structured ASIC, evolution or revolution?, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA [doi>10.1145/981066.981088]
• 53: Xilinx website. www.xilinx.com.
• 54: I. Xilinx. Virtex-II Pro and Virtex-II Pro X FPGA user guide. www.xilinx.com.
• 55: X. Xiong, Y. Hanein, J. Fang, Y. Wang, W. Wang, D. Schwartz, and K. Böhringer. Controlled multibatch self-assembly of microdevices. 12, 2003.
• 56: Zao Yang , K.-T. Cheng , K. L. Tai, A New Bare Die Test Methodology, Proceedings of the 1999 17TH IEEE VLSI Test Symposium, p.290, April 26-30, 1999
• 57: H.-J. J. Yeh and J. S. Smith. Fluidic assembly for the integration of GaAs light-emitting diodes on Si substrates. 6, 1994.
• 58: Behrooz Zahiri, Structured ASICs: Opportunities and Challenges, Proceedings of the 21st International Conference on Computer Design, p.404, October 13-15, 2003
• 59: Zyvex nanotechnology website. http://www.zyvex.com.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Topology (e.g., bus, point-to-point); Interfaces

General Terms:
Design, Performance

Keywords:
chip assembly, design re-use, interconnect design