skip to main content
article

Automated design of application specific superscalar processors: an analytical approach

Published: 09 June 2007 Publication History

Abstract

Analytical modeling is applied to the automated design of application-specific superscalar processors. Using an analytical method bridges the gap between the size of the design space and the time required for detailed cycle-accurate simulations. The proposed design framework takes as inputs the design targets (upper bounds on execution time, area, and energy), design alternatives, and one or more application programs. The output is the set of out-of-order superscalar processors that are Pareto-optimal with respect to performance-energy-area. The core of the new design framework is made up of analytical performance and energy activity models, and an analytical model-based design optimization process.
For a set of benchmark programs and a design space of 2000 designs, the design framework arrives at all performance-energy-area Pareto-optimal design points within 16 minutes on a 2 GHz Pentium-4. In contrast, it is estimated that a naíve cycle-accurate simulation-based exhaustive search would require at least two months to arrive at the Pareto-optimal design points for the same design space.

References

[1]
IBM, "PowerPC 440 Processor Core," available at http://www-306.ibm.com/.
[2]
T. M. Conte, "Systematic Computer Architecture Proto-typing," PhD Thesis: University of Illinois, 1992.
[3]
V. Kathail, S. Aditya, R. Schreiber, B. R. Rau, D. C. Cronquist, and M. Sivaraman, "PICO: Automatically designing custom computers," IEEE Computer, Sept. 2002, pp. 39--47.
[4]
B. Kumar and E. S. Davidson, "Computer System Design Using a Hierarchical Approach to Performance Evaluation," Communications of the ACM, vol. 23, 1980, pp. 511--521.
[5]
M. A. Bhatti, Practical Optimization Methods with Mathematica Applications: Springer Verlag, 2000.
[6]
S. Kirkpatrick, C. Gellat, and M. Vecchi, "Optimization by Simulated Annealing," Science, vol. 220--4598, 1983, pp. 671--680.
[7]
E. Perelman, G. Hamerly, and B. Calder, "Picking Statistically Valid and Early Simulation Points," International Conference on Parallel Architectures and Compilation Techniques, 2003, pp. 244--255.
[8]
R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe, "SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling," International Symposium on Computer Architecture, 2003, pp. 84--97.
[9]
L. Eeckhout, "Accurate Statistical Workload Modeling," PhD Thesis: University of Gent, 2002.
[10]
S. Nussbaum and J. E. Smith, "Modeling Superscalar Processors via Statistical Simulation," International Conference on Parallel Architectures and Compilation Techniques, 2001, pp. 15--24.
[11]
M. Oskin, F. T. Chong, and M. Farrens, "HLS: combining statistical and symbolic simulation to guide microprocessor designs," International Symposium on Com--puter Architecture, 2000, pp. 71--82.
[12]
P. Michaud, A. Seznec, and S. Jourdan, "An Exploration of Instruction Fetch Requirement in Out-Of-Order Superscalar Processors," International Journal of Parallel Processing, vol. 29--1,2001, pp. 35--38.
[13]
D. B. Noonburg and J. P. Shen, "Theoretical Modeling of Superscalar Processor Performance," International Symposium on Microarchitecture, 1994, pp. 52--62.
[14]
E. Riseman and C. Foster, "The Inhibition of Potential Parallelism by Conditional Jumps," IEEE Trans. on Computer Architectures, vol. C--21, 1972, pp. 1405--1411.
[15]
T. Taha and D. S. Wills, "An Instruction Throughput Model of Superscalar Processors," International Work-shop on Rapid Systems Prototyping, 2003, pp. 156--163.
[16]
M. D. Hill and A. J. Smith, "Evaluating Associativity in CPU Caches," IEEE Transactions on Computers, 1989, pp. 1612--1630.
[17]
T. Karkhanis and J. E. Smith, "A First-Order Superscalar Processor Model," International Symposium on Computer Architecture, 2004, pp. 338--349.
[18]
"Computer Hardware Understanding Development Tools 2.0 Reference Guide for MacOS X," July 2002.
[19]
J. M. Tendler, et. al., "IBM Power 4: System Microarchitecture," IBM Journal of Research and Development, 2002, pp. 5--26.
[20]
S. Kachigan, Statistical Analysis. New York: Radius Press, 1986.
[21]
D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: a framework for architectural-level power analysis and optimizations," International Symposium on Computer Architecture, 2000, pp. 83--94.
[22]
J. M. Mulder and M. Flynn, "An Area Model for On-Chip Memories and its Application," IEEE Journal of Solid-State Circuits, vol. 26, 1991, pp. 98--106.
[23]
M. J. Flynn, Computer Architecture: Pipelined and Parallel Processor Design: Jones and Bartlett Publishers, 1995.
[24]
E. Ipek, et al., "Efficiently Exploiting Architectural Design Spaces via Predictive Modeling," Architectural Support For Programming Languages and Operating Systems, 2006, pp. 195--206.
[25]
S. Eyerman, J. Smith, and L. Eeckhout, "Characterizing the Branch Misprediction Penalty", International Symposium on Performance Analysis of Systems and Software, 2006, pp. 48--58.
[26]
S. Eyerman, et al., "A Performance Counter Architecture for Computing Accurate CPI Components," Architectural Support For Programming Languages and Operating Systems, 2006, pp. 175--174.

Cited By

View all
  • (2024)Top-Down Microarchitecture Analysis Approximation Based on Performance Counter Architecture for SiFive RISC-V ProcessorsProceedings of the SC '24 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis10.1109/SCW63240.2024.00208(1666-1675)Online publication date: 17-Nov-2024
  • (2024)Bus and Memory ArchitecturesHandbook of Computer Architecture10.1007/978-981-97-9314-3_68(201-212)Online publication date: 21-Dec-2024
  • (2024)Bus and Memory ArchitecturesHandbook of Computer Architecture10.1007/978-981-15-6401-7_68-1(1-12)Online publication date: 17-Sep-2024
  • Show More Cited By

Index Terms

  1. Automated design of application specific superscalar processors: an analytical approach

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 35, Issue 2
    May 2007
    527 pages
    ISSN:0163-5964
    DOI:10.1145/1273440
    Issue’s Table of Contents
    • cover image ACM Conferences
      ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture
      June 2007
      542 pages
      ISBN:9781595937063
      DOI:10.1145/1250662
      • General Chair:
      • Dean Tullsen,
      • Program Chair:
      • Brad Calder
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 09 June 2007
    Published in SIGARCH Volume 35, Issue 2

    Check for updates

    Author Tags

    1. analytical model
    2. application specific processors
    3. design optimization
    4. energy model
    5. performance model

    Qualifiers

    • Article

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)33
    • Downloads (Last 6 weeks)6
    Reflects downloads up to 13 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2024)Top-Down Microarchitecture Analysis Approximation Based on Performance Counter Architecture for SiFive RISC-V ProcessorsProceedings of the SC '24 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis10.1109/SCW63240.2024.00208(1666-1675)Online publication date: 17-Nov-2024
    • (2024)Bus and Memory ArchitecturesHandbook of Computer Architecture10.1007/978-981-97-9314-3_68(201-212)Online publication date: 21-Dec-2024
    • (2024)Bus and Memory ArchitecturesHandbook of Computer Architecture10.1007/978-981-15-6401-7_68-1(1-12)Online publication date: 17-Sep-2024
    • (2021)Mathematical Modelling of an Application Specific Processor Architecture with Power Optimization2021 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE)10.1109/WIECON-ECE54711.2021.9829608(55-58)Online publication date: 4-Dec-2021
    • (2020)SecSchedProceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques10.1145/3410463.3414631(229-240)Online publication date: 30-Sep-2020
    • (2019)Accelerating the Analytical Modeling of Memory Level Parallelism by the Probability Analysis2019 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM)10.1109/PACRIM47961.2019.8985073(1-6)Online publication date: Aug-2019
    • (2018)Analytic Multi-Core Processor Model for Fast Design-Space ExplorationIEEE Transactions on Computers10.1109/TC.2017.278023967:6(755-770)Online publication date: 1-Jun-2018
    • (2018)Processor Design Space Exploration via Statistical Sampling and Semi-Supervised Ensemble LearningIEEE Access10.1109/ACCESS.2018.28310796(25495-25505)Online publication date: 2018
    • (2017)AFECProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130392(55-60)Online publication date: 27-Mar-2017
    • (2017)AFEC: An analytical framework for evaluating cache performance in out-of-order processorsDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7926958(55-60)Online publication date: Mar-2017
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media