Profile-driven energy reduction in network-on-chips

ABSTRACT

Reducing energy consumption of a Network-on-Chip (NoC) is a critical design goal, especially for power-constrained embedded systems.In response, prior research has proposed several circuit/architectural level mechanisms to reduce NoC power consumption. This paper considers the problem from a different perspective and demonstrates that compiler analysis can be very helpful for enhancing the effectiveness of a hardware-based link power management mechanism by increasing the duration of communication links' idle periods. The proposed profile-based approach achieves its goal by maximizing the communication link reuse through compiler-directed, static message re-routing. That is, it clusters the required data communications into a small set of communication links at any given time, which increases the idle periods for the remaining communication links in the network. This helps hardware shut down more communication links and their corresponding buffers to reduce leakage power. The current experimental evaluation, with twelve data-intensive embedded applications, shows that the proposed profile-driven compiler approach reduces leakage energy by more than 35% (on average) as compared to a pure hardware-based link power management scheme.

REFERENCES

• 1: Giuseppe Ascia , Vincenzo Catania , Maurizio Palesi, Multi-objective mapping for mesh-based NoC architectures, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden [doi>10.1145/1016720.1016765]
• 2: Luca Benini , Giovanni De Micheli, Powering networks on chips: energy-efficient and reliable interconnect design for SoCs, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada [doi>10.1145/500001.500009]
• 3: Guangyu Chen , Feihui Li , Mahmut Kandemir, Compiler-directed channel allocation for saving power in on-chip networks, Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.194-205, January 11-13, 2006, Charleston, South Carolina, USA
• 4: Guangyu Chen , Feihui Li , Mahmut Kandemir , Mary Jane Irwin, Reducing NoC energy consumption through compiler-directed channel voltage scaling, Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation, June 11-14, 2006, Ottawa, Ontario, Canada
• 5: Xuning Chen , Li-Shiuan Peh, Leakage power modeling and optimization in interconnection networks, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871531]
• 6: W. J. Dally , C. L. Seitz, Deadlock-Free Message Routing in Multiprocessor Interconnection Networks, IEEE Transactions on Computers, v.36 n.5, p.547-553, May 1987 [doi>10.1109/TC.1987.1676939]
• 7: William J. Dally , Brian Towles, Route packets, not wires: on-chip inteconnection networks, Proceedings of the 38th conference on Design automation, p.684-689, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379048]
• 8: José Duato, A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks, IEEE Transactions on Parallel and Distributed Systems, v.4 n.12, p.1320-1331, December 1993 [doi>10.1109/71.250114 ]
• 9: Jose Duato , Sudhakar Yalamanchili , Ni Lionel, Interconnection Networks: An Engineering Approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 2002
• 10: Noel Eisley , Li-Shiuan Peh, High-level power analysis for on-chip networks, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA [doi>10.1145/1023833.1023849]
• 11: Peter S. Magnusson , Magnus Christensson , Jesper Eskilson , Daniel Forsgren , Gustav Hållberg , Johan Högberg , Fredrik Larsson , Andreas Moestedt , Bengt Werner, Simics: A Full System Simulation Platform, Computer, v.35 n.2, p.50-58, February 2002 [doi>10.1109/2.982916 ]
• 12: Andreas Hansson , Kees Goossens , Andrei Rǎdulescu, A unified approach to constrained mapping and routing on network-on-chip architectures, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA [doi>10.1145/1084834.1084857]
• 13: J. Hu and R. Marculescu. Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 24(4), Apr. 2005.
• 14: Antoine Jalabert , Srinivasan Murali , Luca Benini , Giovanni De Micheli, ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip, Proceedings of the conference on Design, automation and test in Europe, p.20884, February 16-20, 2004
• 15: E. J. Kim , K. H. Yum , G. M. Link , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , M. Yousif , C. R. Das, Energy optimization techniques in cluster interconnects, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871620]
• 16: http://cares.icsl.ucla.edu/MediaBench/.
• 17: http://www.eecs.umich.edu/mibench/.
• 18: Shubhendu S. Mukherjee , Peter Bannon , Steven Lang , Aaron Spink , David Webb, The Alpha 21364 Network Architecture, IEEE Micro, v.22 n.1, p.26-35, January 2002 [doi>10.1109/40.988687 ]
• 19: Ramadass Nagarajan , Sundeep K. Kushwaha , Doug Burger , Kathryn S. McKinley , Calvin Lin , Stephen W. Keckler, Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures, Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, p.74-84, September 29-October 03, 2004 [doi>10.1109/PACT.2004.26]
• 20: Umit Y. Ogras , Jingcao Hu , Radu Marculescu, Key research problems in NoC design: a holistic perspective, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA [doi>10.1145/1084834.1084856]
• 21: C. S. Patel, Power constrained design of multiprocessor interconnection networks, Proceedings of the 1997 International Conference on Computer Design (ICCD '97), p.408, October 12-15, 1997
• 22: Vijay Raghunathan , Mani B. Srivastava , Rajesh K. Gupta, A survey of techniques for energy efficient on-chip communication, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.776059]
• 23: Li Shang , Li-Shiuan Peh , Niraj K. Jha, Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks, Proceedings of the 9th International Symposium on High-Performance Computer Architecture, p.91, February 08-12, 2003
• 24: Dongkun Shin , Jihong Kim, Power-aware communication optimization for networks-on-chips with voltage scalable links, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden [doi>10.1145/1016720.1016763]
• 25: T. Simunic , S. Boyd, Managing Power Consumption in Networks on Chip, Proceedings of the conference on Design, automation and test in Europe, p.110, March 04-08, 2002
• 26: V. Soteriou and L.-S. Peh. Dynamic power management for power optimization of interconnection networks using on/off links. In Proc. Symposium on High Performance Interconnects, 2003.
• 27: Vassos Soteriou , Li-Shiuan Peh, Design-Space Exploration of Power-Aware On/Off Interconnection Networks, Proceedings of the IEEE International Conference on Computer Design (ICCD'04), p.510-517, October 11-13, 2004
• 28: Michael Bedford Taylor , Jason Kim , Jason Miller , David Wentzlaff , Fae Ghodrat , Ben Greenwald , Henry Hoffman , Paul Johnson , Jae-Wook Lee , Walter Lee , Albert Ma , Arvind Saraf , Mark Seneski , Nathan Shnidman , Volker Strumpen , Matt Frank , Saman Amarasinghe , Anant Agarwal, The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs, IEEE Micro, v.22 n.2, p.25-35, March 2002 [doi>10.1109/MM.2002.997877 ]
• 29: http://www-unix.mcs.anl.gov/mpi/.
• 30: http://www.ece.northwestern.edu/cpdc/Paradigm/Paradigm.html.
• 31: Hang-Sheng Wang , Xinping Zhu , Li-Shiuan Peh , Sharad Malik, Orion: a power-performance simulator for interconnection networks, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 32: Frédéric Worm , Paolo Ienne , Patrick Thiran , Giovanni De Micheli, An adaptive low-power transmission scheme for on-chip networks, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan [doi>10.1145/581199.581221]
• 33: N.D. Zervas, K. Masselos, and C. Goutis. Code transformations for embedded multimedia applications: impact on power and performance. In Proc. ISCA Power-Driven Microarchitecture Workshop, 1998.

INDEX TERMS

Primary Classification:
  D. Software
  D.3 PROGRAMMING LANGUAGES
      D.3.4 Processors
          Subjects: Compilers

General Terms:
Algorithms, Experimentation, Management

Keywords:
Network-on-Chip, compiler, power, routing