Optimizing software cache performance of packet processing applications
Abstract
References
Index Terms
- Optimizing software cache performance of packet processing applications
Recommendations
Optimizing software cache performance of packet processing applications
LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systemsNetwork processors (NPs) are widely used in many types of networking equipment due to their high performance and flexibility. For most NPs, software cache is used instead of hardware cache due to the chip area, cost and power constraints. Therefore, ...
Cache Architecture for High-Speed Multidimensional Packet Processing
ICICSE '12: Proceedings of the 2012 Sixth International Conference on Internet Computing for Science and EngineeringIn this paper, we implement a multi-dimensional packet classification that is based on the hierarchical binary prefix search. We first implement the multi-dimensional binary prefix search packet classification on Intel IXP2400 Network Processor that ...
Comments
Information & Contributors
Information
Published In
![cover image ACM SIGPLAN Notices](/cms/asset/2c7a2b6e-0f12-4ea5-b417-aca069ba5320/1273444.cover.gif)
- June 2007258 pages
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Check for updates
Author Tags
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations4Total Citations
- 371Total Downloads
- Downloads (Last 12 months)3
- Downloads (Last 6 weeks)0
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in