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High-level test synthesis for delay fault testability

Published: 16 April 2007 Publication History

Abstract

A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embedded modules, guarantees 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay fault coverage is usually attributed to the fact that two-pattern test for delay testing cannot be delivered to modules under test in consecutive cycles. To solve the problem, we propose an HLTS method that ensures valid test pairs can be sent to each module through synthesized circuit hierarchy. Experimental results show that this method achieves 100% fault coverage for transition faults in functional units, while the fault coverage in circuits synthesized by LEA-based allocation algorithm is rather poor. The area overhead due to this method ranges from 2% to 10% for 16-bit datapaths.

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  1. High-level test synthesis for delay fault testability

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    cover image ACM Conferences
    DATE '07: Proceedings of the conference on Design, automation and test in Europe
    April 2007
    1741 pages
    ISBN:9783981080124

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    EDA Consortium

    San Jose, CA, United States

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    Published: 16 April 2007

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    • The Russian Academy of Sciences
    DATE07: Design, Automation and Test in Europe
    April 16 - 20, 2007
    Nice, France

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    Overall Acceptance Rate 518 of 1,794 submissions, 29%

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    • (2019)Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based DesignACM Transactions on Design Automation of Electronic Systems10.1145/332506624:4(1-19)Online publication date: 29-May-2019

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