Article

Toward a scalable test methodology for 2D-mesh Network-on-Chips

Authors:

Johnny ÖbergAuthors Info & Claims

DATE '07: Proceedings of the conference on Design, automation and test in Europe

Pages 367 - 372

Published: 16 April 2007 Publication History

Abstract

This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%.

References

[1]

M. Millberg, E. Nilsson, R. Thid and A. Jantch. A Guaranteed bandwidth using looped containers in temporary disjoint networks within the Nostrum network on chip. Proc. DATE, pp 890--895 Vol. 2, 2004.

Digital Library

[2]

Standard IEEE 1500. Standard Testability Method for Embedded Core-based Integrated Circuits. IEEE 2005.

[3]

A. M. Amory, E. Brião, É Cota, M. Lubaszewski, F. G. Moraes. A Scalable Test Strategy for Network-on-Chip Routers. Proc. of ITC 2005.

[4]

B. Vermeulen, J. Dielissen, and K. Goossens. Bringing Communication Networks on a Chip: Test and Verification Implications. IEEE Communications Magazine, vol. 41--9, 2003, pp. 74--81.

Digital Library

[5]

Y. Zorian. Embedded Infrastructure IP for SOC Yield Improvement. DAC 02, pages 709--712.

Digital Library

[6]

K. Arabi. Logic BIST and Scan Test Techniques for Multiple Identical Blocks. IEEE VLSI Test Symposium, 2002, pp. 60--68.

Digital Library

[7]

R.Ubar and J Raik. Testing Strategies for Network on Chip. Book: Network on Chip, A. Jantsch and H. Tenhunen, Eds. Kluwer Academic Publisher, 2003, pp. 131--152.

Digital Library

[8]

C. Aktouf. A Complete Strategy for Testing an on-Chip Multiprocessor Architecture. IEEE Design & test of Computers, vol. 19--1, 2002, pp. 18--28.

Digital Library

[9]

C. A. Zeferino, M. E. Kreutz, L. Carro and A. A. Susin. A Study on Communication Issues for System-on-Chip. Proceedings of the 15^th Symposium on Integrated Circuits and System Design (SBCCI), 2002.

Digital Library

[10]

Panda et al. Design, Synthesis, and Test of Networks on Chips. IEEE D&T, vol. 22, issue 8 2005, pp404--413.

Digital Library

[11]

K. Petersén, J Öberg. Utilizing NoC Switches as BIST-structures in 2D-Mesh Network-on-Chip. Future Interconnects and Network on Chip Workshop, 2006.

[12]

Y. Zorian. Testing the monster chip. IEEE Spectrum, July 1999, pages 54--60.

Digital Library

[13]

Y. Zorian. Embedded Memory Test and Repair: Infrastructure IP for SoC Yield. International Test Conference 2002, pages 340--349.

Digital Library

[14]

C. Grecu, P. Pande, B. Wang, A. Ivanov, R. Saleh. Methodologies and Algorithm for Testing Switch-Based NoC Interconnects. IEEE DFT 2005, pages 238--246.

Digital Library

[15]

E. Cota et al. The Impact of NoC Reuse on the Testing of Core-based Systems. VTS 2003, pages 128--133.

Digital Library

[16]

C. Grecu, P. Pande, A. Ivanov, R. Saleh. BIST for Network-on-Chip Interconnect Infrastructures.

Cited By

Manna KSagar CChattopadhyay SSengupta I(2019)Thermal-aware Test Scheduling Strategy for Network-on-Chip based SystemsACM Journal on Emerging Technologies in Computing Systems10.1145/324105015:1(1-27)Online publication date: 8-Feb-2019
https://dl.acm.org/doi/10.1145/3241050
Xiang DChakrabarty KFujiwara H(2018)Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip TestingACM Transactions on Design Automation of Electronic Systems10.1145/324321423:6(1-23)Online publication date: 6-Dec-2018
https://dl.acm.org/doi/10.1145/3243214
Nourmandi-Pour RKhadem-Zadeh AMasoud Rahmani A(2018)An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chipMicroelectronics Journal10.1016/j.mejo.2010.04.01441:7(417-429)Online publication date: 26-Dec-2018
https://dl.acm.org/doi/10.1016/j.mejo.2010.04.014
Show More Cited By

Toward a scalable test methodology for 2D-mesh Network-on-Chips
1. Hardware

Recommendations

Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks

Using a packet-based built-in self test for RAM cores in mesh-based networks on chip (NoC) can reduce the BIST circuit's area cost. The proposed scheme reuses the NoC to transport test patterns to RAM such that routing doesn't limit the number of RAM ...
Achieving scalable mutation-based generation of whole test suites

Without complete formal specification, automatically generated software tests need to be manually checked in order to detect faults. This makes it desirable to produce the strongest possible test set while keeping the number of tests as small as ...
A Methodology for Test Selection

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '07: Proceedings of the conference on Design, automation and test in Europe

April 2007

1741 pages

ISBN:9783981080124

General Chair:
Rudy Lauwereins
IMEC and KULeuven, Belgium
,
Program Chair:
Jan Madsen
DTU, Denmark

Sponsors

The EDA Consortium
EDAA: European Design Automation Association
ECSI
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 16 April 2007

Check for updates

Qualifiers

Article

Conference

DATE07

Sponsor:

EDAA
SIGDA
The Russian Academy of Sciences

DATE07: Design, Automation and Test in Europe

April 16 - 20, 2007

Nice, France

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25

Sponsor:
sigda

Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

7
Total Citations
View Citations
250
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 05 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Manna KSagar CChattopadhyay SSengupta I(2019)Thermal-aware Test Scheduling Strategy for Network-on-Chip based SystemsACM Journal on Emerging Technologies in Computing Systems10.1145/324105015:1(1-27)Online publication date: 8-Feb-2019
https://dl.acm.org/doi/10.1145/3241050
Xiang DChakrabarty KFujiwara H(2018)Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip TestingACM Transactions on Design Automation of Electronic Systems10.1145/324321423:6(1-23)Online publication date: 6-Dec-2018
https://dl.acm.org/doi/10.1145/3243214
Nourmandi-Pour RKhadem-Zadeh AMasoud Rahmani A(2018)An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chipMicroelectronics Journal10.1016/j.mejo.2010.04.01441:7(417-429)Online publication date: 26-Dec-2018
https://dl.acm.org/doi/10.1016/j.mejo.2010.04.014
Aghaei BKhademzadeh AReshadi MBadie K(2017)Link TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5646-033:2(209-225)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1007/s10836-017-5646-0
Xiang DShen K(2016)A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect TestingACM Transactions on Design Automation of Electronic Systems10.1145/282150621:2(1-23)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2821506
Ghiribaldi ALudovici DTriviño FStrano AFlich JSánchez JAlfaro FFavalli MBertozzi D(2013)A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCsACM Transactions on Embedded Computing Systems10.1145/2485984.248599412:4(1-29)Online publication date: 3-Jul-2013
https://dl.acm.org/doi/10.1145/2485984.2485994
Minhass WÖberg JSander ILindh L(2009)Design and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL supportProceedings of the 6th FPGAworld Conference10.1145/1667520.1667527(52-57)Online publication date: 10-Sep-2009
https://dl.acm.org/doi/10.1145/1667520.1667527

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten