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Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs

Published: 16 April 2007 Publication History

Abstract

Carbon Nanotube Field Effect Transistors (CNTFET) are promising nano-scaled devices for implementing high performance, very dense and low power circuits. The core of a CNTFET is a carbon nanotube. Its conductance property is determined by the so-called chirality of the tube; chirality is difficult to control during manufacturing. This results in conducting (metallic) nanotubes and defective CNTFETs similar to stuck-on (SON or source-drain short) faults, as encountered in classical MOS devices. This paper studies this phenomenon by using layout information and presents modeling and detection methodologies for nano-scaled defects arising from the presence of metallic carbon nanotubes. For CNTFET-based circuits (e.g. intramolecular), these defects are analyzed using a traditional stuck-at fault model. This analysis is applicable to primitive and complex gates. Simulation results are presented for detecting modeled metallic nanotube faults in CNTFETs using a single stuck-at fault test set. A high coverage is achieved (~98%).

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Cited By

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  • (2016)A Novel Test Method for Metallic CNTs in CNFET-Based SRAMsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.251290935:7(1192-1205)Online publication date: 1-Jul-2016
  • (2015)Jump test for metallic CNTs in CNFET-based SRAMProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744864(1-6)Online publication date: 7-Jun-2015
  1. Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs

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    cover image ACM Conferences
    DATE '07: Proceedings of the conference on Design, automation and test in Europe
    April 2007
    1741 pages
    ISBN:9783981080124

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    EDA Consortium

    San Jose, CA, United States

    Publication History

    Published: 16 April 2007

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    Author Tags

    1. CNT
    2. CNTFET
    3. carbon nanotube
    4. defect modeling
    5. fault detection
    6. nanotechnology

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    DATE07
    Sponsor:
    • EDAA
    • SIGDA
    • The Russian Academy of Sciences
    DATE07: Design, Automation and Test in Europe
    April 16 - 20, 2007
    Nice, France

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    Overall Acceptance Rate 518 of 1,794 submissions, 29%

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    • (2016)A Novel Test Method for Metallic CNTs in CNFET-Based SRAMsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.251290935:7(1192-1205)Online publication date: 1-Jul-2016
    • (2015)Jump test for metallic CNTs in CNFET-based SRAMProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744864(1-6)Online publication date: 7-Jun-2015

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