Analytical router modeling for networks-on-chip performance analysis

ABSTRACT

Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we first present a generalized router model and then utilize this novel model for doing NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.

References

1. L. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm," IEEE Computer, 35(1), Jan. 2002
2. D. Bertsekas and R. Gallager, Data Networks. Prentice Hall, 1992.
3. W. J. Dally. "Performance analysis of k-ary n-cube interconnection networks," IEEE Trans. on Computers, 39(6), June, 1990.
4. W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003.
5. J. Dielissen, et al., "Concepts and implementation of the Philips network-on-chip," in Proc. IP-based SoC Design, Nov. 2003.
6. J. Draper and J. Ghosh, "A comprehensive analytical model for wormhole routing in multicomputer systems," Journal of Parallel and Distributed Computing, 23(2), Nov. 1994.
7. W. Guan, W. Tsai, and D. Blough, "An analytical model for wormhole routing in multicomputer interconnection networks," in Proc. Intl. Parallel Processing Symposium, Apr., 1993.
8. Z. Guz, et. al., "Efficient link capacity and QoS design for wormhole network-on-chip," in Proc. DATE, March 2006.
9. J. Hu and R. Marculescu, "Energy- and performance-aware mapping for regular NoC architectures," IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, 24(4), Apr. 2005.
10. J. Hu, et. al., "System-level buffer allocation for application-specific networks-on-chip router design," IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, 25(12), Dec. 2006.
11. P. Hu and L. Kleinrock, "An analytical model for wormhole routing with finite size input buffers," 15th Intl. Teletraffic Congress, June 1997.
12. P. Lieverse, et. al., "A methodology for architecture exploration of heterogeneous signal processing systems," Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 29(3), Nov. 2001.
13. M. Millberg, E. Nilsson, R. Thid and A. Jantsch, "Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip," in Proc. DATE, Feb. 2004.
14. S. Murali and G. De Micheli, "Bandwidth-constrained mapping of cores onto NoC architectures," in Proc. DATE, March 2004.
15. U. Y. Ogras and R. Marculescu, "'It's a small world after all': NoC performance optimization via long-range link insertion," IEEE Trans, on VLSI, 14(7), 2006.
16. M. Ould-Khaoua and H. Sarbazi-Azad, "An analytical model of adaptive wormhole routing in hypercubes in the presence of hot spot traffic," IEEE Trans on Parallel and Distributed Systems, 12(3), March, 2001.
17. H. Takagi, Queueing Analysis, Vol. 2: Finite Systems. Elsevier, 1993.
18. G. Varatkar and R. Marculescu, "On-Chip traffic modeling and synthesis for MPEG-2 video applications," IEEE Trans, on VLSI, 12(1), 2004.

• General and reference

  • Cross-computing tools and techniques

• Networks

• Social and professional topics

  • Professional topics

    • Computing profession