Christian Sauer
ABSTRACT
The Network-Optimized Versatile Architecture Platform (NOVA) encapsulates embedded cores, tightly and loosely coupled coprocessors, on-chip memories, and I/O interfaces by special sockets that provide a common packet passing and communication infrastructure. To ease the programming of the heterogeneous multiprocessor target for the application developer, a component based framework is used for describing packet processing applications in a natural and productive way. Leveraging identical application and hardware communication semantics, code generators and off-the-shelf tool chains can automate the software implementation process. Using a prototype with four processing cores we quantify the overhead of modularity and programmability for the platform.
- M. K. Chen, X. F. Li, et al.: Shangri-La: Achieving High Performance from Compiled Network Applications while Enabling Ease of Programming, PLDI, June 2005 Google Scholar
Digital Library
- B. Chen, R. Morris: Flexible Control of Parallelism in a Multiprocessor PC Router, USENIX, June 2001 Google ScholarDigital Library
- R. E. Gonzalez: Xtensa: a configurable and extensible processor, IEEE Micro, 20(2), Mar./Apr. 2000 Google ScholarDigital Library
- M. Gries, C. Kulkarni, et al.: Comparing Analytical Modeling with Simulation for Network Processors, DATE, March 2003 Google ScholarDigital Library
- K. Keutzer, S. Malik, et al.: System Level Design: Orthogonalization of Concerns and Platform-Based Design. IEEE Trans, on CAD of Int. Circuits and Systems, 19(12), Dec. 2000 Google ScholarDigital Library
- E. Kohler, R. Morris, et al.: The Click modular router, ACM Transactions on Computer Systems, 18(3), August 2000 Google ScholarDigital Library
- P. Paulin, C. Pilkington, E. Bensoudane: StepNP: A System-Level Exploration Platform for Network Processors, IEEE Design and Test of Computers, 19(6), Nov./Dec. 2002 Google ScholarDigital Library
- C. Sauer, M. Gries, S. Sonntag: Modular Reference Implementation of an IP-DSLAM, ISCC, Spain, June 2005 Google ScholarDigital Library
- C. Sauer, M. Gries, S. Sonntag: Modular Domain-Specific Implementation and Exploration Framework for Embedded Software Platforms, DAC, June 2005 Google ScholarDigital Library
- N. Shah, W. Plishker, K. Keutzer: NP-Click: A Programming Model for the Intel IXP1200, Network Processor Design, vol. 2, Morgan Kaufmann, Nov. 2003Google Scholar
- B. Wheeler, L. Gwennap: A Guide to Network Processors, 7th Edition, The Linley Group, Dec. 2005Google Scholar
- Agilent Technologies: JTC 003: Mixed packet size throughput, Journal of Internet Test Methodologies, Sept. 2004Google Scholar
Recommendations
NOVA: A Functional Language for Data Parallelism
ARRAY'14: Proceedings of ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array ProgrammingFunctional languages provide a solid foundation on which complex optimization passes can be designed to exploit parallelism available in the underlying system. Their mathematical foundations enable high-level optimizations that would be impossible in ...
Nuclear Reactor Simulations on OpenCL FPGA Platform
FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysField-programmable gate arrays (FPGAs) are becoming a promising choice as a heterogeneous computing component for scientific computing when floating-point optimized architectures are added to the current FPGAs. The maturing high-level synthesis (HLS) ...
Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics
DATE '07: Proceedings of the conference on Design, automation and test in EuropeThis paper presents the RECOPS project that aims to study the use of reconfiguration in military applications. The project explores the new potentials and possibilities offered by reconfigurable components like FPGA. It identifies specificities related ...
Comments