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Efficient buffer capacity and scheduler setting computation for soft real-time stream processing applications
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Source ACM International Conference Proceeding Series; Vol. 235 archive
Proceedingsof the 10th international workshop on Software & compilers for embedded systems table of contents
Nice, France
SESSION: Stream- and data-flow based computing table of contents
Pages: 1 - 10  
Year of Publication: 2007
Authors
Marco Bekooij  NXP semiconductors, Eindhoven, The Netherlands
Maarten Wiggers  University of Twente, Enschede, The Netherlands
Jef van Meerbergen  Philips Research, Eindhoven, The Netherlands and Eindhoven University of Technology, Eindhoven, The Netherlands
Sponsors
: Artist2 European NoE
: ACE Associated Compiler Experts bv
SIGBED: ACM Special Interest Group on Embedded Systems
: European Design and Automation Association, EDAA
Publisher
ACM  New York, NY, USA
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ABSTRACT

Soft real-time applications that process data streams can often be intuitively described as dataflow process networks. In this paper we present a novel analysis technique to compute conservative estimates of the required buffer capacities in such process networks. With the same analysis technique scheduler settings can be verified. Unlike many other soft real-time analysis techniques, it is guaranteed that the desired throughput is obtained for the input stream that is used to characterize the application.

Experiments with artificial test-cases indicate that the computed FIFO capacities become more conservative if the desired throughput gets closer to the maximum throughput. The run-time of our algorithm for an H263 video decoder test-case was 14 seconds.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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G. Bilsen, M. Engels, R. Lauwereins, and J. Peperstraete. Cyclo-Static Dataflow. IEEE Transactions on Signal Processing, 44(2):397--408, 1996.
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E. A. Lee and T. M. Parks. Dataflow Process Networks. Proceedings of the IEEE, 83(5), May 1995.
 
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C. W. Mercer, S. Savage, and H. Tokuda. Processor Capacity Reserves: Operating System Support for Multimedia Systems. In Proc. IEEE International Conference of Multimedia Computing and Systems. IEEE Computer Society Press, 1994.
 
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B. D. Theelen. Performance Modelling for System-Level Design. PhD thesis, Eindhoven University of Technology, 2004.
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M. Wiggers, M. Bekooij, and G. Smit. Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs. Technical Report TR-CTIT-06-70, University of Twente, November 2006.

Collaborative Colleagues:
Marco Bekooij: colleagues
Maarten Wiggers: colleagues
Jef van Meerbergen: colleagues